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Rev 326 | Rev 327 | ||
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Line 49... | Line 49... | ||
49 | */ |
49 | */ |
50 | 50 | ||
51 | cpu_priority_high(); |
51 | cpu_priority_high(); |
52 | cp0_status_write(cp0_status_read() & ~ (cp0_status_exl_exception_bit | |
52 | cp0_status_write(cp0_status_read() & ~ (cp0_status_exl_exception_bit | |
53 | cp0_status_um_bit)); |
53 | cp0_status_um_bit)); |
- | 54 | ||
54 | /* Save pstate so that the threads can access it */ |
55 | /* Save pstate so that the threads can access it */ |
- | 56 | /* If THREAD->pstate is set, this is nested exception, |
|
- | 57 | * do not rewrite it |
|
- | 58 | */ |
|
55 | if (THREAD) |
59 | if (THREAD && !THREAD->pstate) |
56 | THREAD->pstate = pstate; |
60 | THREAD->pstate = pstate; |
57 | 61 | ||
58 | /* decode exception number and process the exception */ |
62 | /* decode exception number and process the exception */ |
59 | switch (excno = (cp0_cause_read() >> 2) & 0x1f) { |
63 | switch (excno = (cp0_cause_read() >> 2) & 0x1f) { |
60 | case EXC_Int: |
64 | case EXC_Int: |
Line 62... | Line 66... | ||
62 | break; |
66 | break; |
63 | case EXC_TLBL: |
67 | case EXC_TLBL: |
64 | case EXC_TLBS: |
68 | case EXC_TLBS: |
65 | tlb_invalid(pstate); |
69 | tlb_invalid(pstate); |
66 | break; |
70 | break; |
- | 71 | case EXC_CpU: |
|
- | 72 | #ifdef FPU_LAZY |
|
- | 73 | scheduler_fpu_lazy_request(); |
|
- | 74 | #else |
|
- | 75 | panic("unhandled Coprocessor Unusable Exception\n"); |
|
- | 76 | #endif |
|
- | 77 | break; |
|
67 | case EXC_Mod: |
78 | case EXC_Mod: |
68 | panic("unhandled TLB Modification Exception\n"); |
79 | panic("unhandled TLB Modification Exception\n"); |
69 | break; |
80 | break; |
70 | case EXC_AdEL: |
81 | case EXC_AdEL: |
71 | panic("unhandled Address Error Exception - load or instruction fetch\n"); |
82 | panic("unhandled Address Error Exception - load or instruction fetch\n"); |
Line 85... | Line 96... | ||
85 | epc_shift = 4; |
96 | epc_shift = 4; |
86 | break; |
97 | break; |
87 | case EXC_RI: |
98 | case EXC_RI: |
88 | panic("unhandled Reserved Instruction Exception\n"); |
99 | panic("unhandled Reserved Instruction Exception\n"); |
89 | break; |
100 | break; |
90 | case EXC_CpU: |
- | |
91 | #ifdef FPU_LAZY |
- | |
92 | scheduler_fpu_lazy_request(); |
- | |
93 | #else |
- | |
94 | panic("unhandled Coprocessor Unusable Exception\n"); |
- | |
95 | #endif |
- | |
96 | break; |
- | |
97 | case EXC_Ov: |
101 | case EXC_Ov: |
98 | panic("unhandled Arithmetic Overflow Exception\n"); |
102 | panic("unhandled Arithmetic Overflow Exception\n"); |
99 | break; |
103 | break; |
100 | case EXC_Tr: |
104 | case EXC_Tr: |
101 | panic("unhandled Trap Exception\n"); |
105 | panic("unhandled Trap Exception\n"); |
Line 115... | Line 119... | ||
115 | default: |
119 | default: |
116 | panic("unhandled exception %d\n", excno); |
120 | panic("unhandled exception %d\n", excno); |
117 | } |
121 | } |
118 | 122 | ||
119 | pstate->epc += epc_shift; |
123 | pstate->epc += epc_shift; |
- | 124 | /* Set to NULL, so that we can still support nested |
|
- | 125 | * exceptions |
|
120 | /* Probable not needed, but just for sure that nobody |
126 | * TODO: We should probably set EXL bit before this command, |
121 | * will continue accessing it */ |
127 | * nesting. On the other hand, if some exception occurs between |
- | 128 | * here and ERET, it won't set anything on the pstate anyway. |
|
- | 129 | */ |
|
122 | if (THREAD) |
130 | if (THREAD) |
123 | THREAD->pstate = NULL; |
131 | THREAD->pstate = NULL; |
124 | } |
132 | } |