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29 | #ifndef __mips32_TLB_H__ |
29 | #ifndef __mips32_TLB_H__ |
30 | #define __mips32_TLB_H__ |
30 | #define __mips32_TLB_H__ |
31 | 31 | ||
32 | #include <arch/exception.h> |
32 | #include <arch/exception.h> |
33 | 33 | ||
- | 34 | #define TLB_SIZE 48 |
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- | 35 | ||
- | 36 | #define TLB_WIRED 1 |
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- | 37 | #define TLB_KSTACK_WIRED_INDEX 0 |
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- | 38 | ||
- | 39 | #define TLB_PAGE_MASK_16K (0x3<<13) |
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- | 40 | ||
34 | #define PAGE_UNCACHED 2 |
41 | #define PAGE_UNCACHED 2 |
35 | #define PAGE_CACHEABLE_EXC_WRITE 5 |
42 | #define PAGE_CACHEABLE_EXC_WRITE 5 |
36 | 43 | ||
37 | struct entry_lo { |
44 | struct entry_lo { |
38 | unsigned g : 1; /* global bit */ |
45 | unsigned g : 1; /* global bit */ |
Line 63... | Line 70... | ||
63 | struct page_mask mask; |
70 | struct page_mask mask; |
64 | } __attribute__ ((packed)); |
71 | } __attribute__ ((packed)); |
65 | 72 | ||
66 | typedef struct entry_lo pte_t; |
73 | typedef struct entry_lo pte_t; |
67 | 74 | ||
- | 75 | /** Read Indexed TLB Entry |
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- | 76 | * |
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- | 77 | * Read Indexed TLB Entry. |
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- | 78 | */ |
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- | 79 | static inline void tlbr(void) |
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- | 80 | { |
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- | 81 | __asm__ volatile ("tlbr\n\t"); |
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- | 82 | } |
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- | 83 | ||
- | 84 | /** Write Indexed TLB Entry |
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- | 85 | * |
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- | 86 | * Write Indexed TLB Entry. |
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- | 87 | */ |
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- | 88 | static inline void tlbwi(void) |
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- | 89 | { |
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- | 90 | __asm__ volatile ("tlbwi\n\t"); |
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- | 91 | } |
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- | 92 | ||
- | 93 | /** Write Random TLB Entry |
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- | 94 | * |
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- | 95 | * Write Random TLB Entry. |
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- | 96 | */ |
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- | 97 | static inline void tlbwr(void) |
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- | 98 | { |
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- | 99 | __asm__ volatile ("tlbwr\n\t"); |
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- | 100 | } |
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- | 101 | ||
68 | extern void tlb_invalid(struct exception_regdump *pstate); |
102 | extern void tlb_invalid(struct exception_regdump *pstate); |
69 | extern void tlb_refill(struct exception_regdump *pstate); |
103 | extern void tlb_refill(struct exception_regdump *pstate); |
- | 104 | extern void tlb_modified(struct exception_regdump *pstate); |
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70 | 105 | ||
71 | #endif |
106 | #endif |