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| Rev 391 | Rev 394 | ||
|---|---|---|---|
| Line 44... | Line 44... | ||
| 44 | * NOTE: this implementation is under construction |
44 | * NOTE: this implementation is under construction |
| 45 | * |
45 | * |
| 46 | * Page table layout: |
46 | * Page table layout: |
| 47 | * - 32-bit virtual addresses |
47 | * - 32-bit virtual addresses |
| 48 | * - Offset is 14 bits => pages are 16K long |
48 | * - Offset is 14 bits => pages are 16K long |
| 49 | * - PTE's use the same format as CP0 EntryLo[01] registers => PTE is therefore 4 bytes long |
49 | * - PTE's use similar format as CP0 EntryLo[01] registers => PTE is therefore 4 bytes long |
| - | 50 | * - PTE's make use of CP0 EntryLo's two-bit reserved field for bit W (writable) and bit A (accessed) |
|
| 50 | * - PTL0 has 64 entries (6 bits) |
51 | * - PTL0 has 64 entries (6 bits) |
| 51 | * - PTL1 is not used |
52 | * - PTL1 is not used |
| 52 | * - PTL2 is not used |
53 | * - PTL2 is not used |
| 53 | * - PTL3 has 4096 entries (12 bits) |
54 | * - PTL3 has 4096 entries (12 bits) |
| 54 | */ |
55 | */ |
| 55 | 56 | ||
| 56 | #define PTL0_INDEX_ARCH(vaddr) ((vaddr)>>26) |
57 | #define PTL0_INDEX_ARCH(vaddr) ((vaddr)>>26) |
| 57 | #define PTL1_INDEX_ARCH(vaddr) 0 |
58 | #define PTL1_INDEX_ARCH(vaddr) 0 |
| 58 | #define PTL2_INDEX_ARCH(vaddr) 0 |
59 | #define PTL2_INDEX_ARCH(vaddr) 0 |
| 59 | #define PTL3_INDEX_ARCH(vaddr) (((vaddr)>>12)&0xfff) |
60 | #define PTL3_INDEX_ARCH(vaddr) (((vaddr)>>14)&0x3fff) |
| 60 | 61 | ||
| 61 | #define GET_PTL0_ADDRESS_ARCH() (PTL0) |
62 | #define GET_PTL0_ADDRESS_ARCH() (PTL0) |
| 62 | #define SET_PTL0_ADDRESS_ARCH(ptl0) (PTL0 = (pte_t *)(ptl0)) |
63 | #define SET_PTL0_ADDRESS_ARCH(ptl0) (PTL0 = (pte_t *)(ptl0)) |
| 63 | 64 | ||
| 64 | #define GET_PTL1_ADDRESS_ARCH(ptl0, i) (((pte_t *)(ptl0))[(i)].pfn<<12) |
65 | #define GET_PTL1_ADDRESS_ARCH(ptl0, i) (((pte_t *)(ptl0))[(i)].pfn<<12) |
| Line 95... | Line 96... | ||
| 95 | return ( |
96 | return ( |
| 96 | ((p->c>PAGE_UNCACHED)<<PAGE_CACHEABLE_SHIFT) | |
97 | ((p->c>PAGE_UNCACHED)<<PAGE_CACHEABLE_SHIFT) | |
| 97 | ((!p->v)<<PAGE_PRESENT_SHIFT) | |
98 | ((!p->v)<<PAGE_PRESENT_SHIFT) | |
| 98 | (1<<PAGE_USER_SHIFT) | |
99 | (1<<PAGE_USER_SHIFT) | |
| 99 | (1<<PAGE_READ_SHIFT) | |
100 | (1<<PAGE_READ_SHIFT) | |
| 100 | ((p->d)<<PAGE_WRITE_SHIFT) | |
101 | ((p->w)<<PAGE_WRITE_SHIFT) | |
| 101 | (1<<PAGE_EXEC_SHIFT) |
102 | (1<<PAGE_EXEC_SHIFT) |
| 102 | ); |
103 | ); |
| 103 | 104 | ||
| 104 | } |
105 | } |
| 105 | 106 | ||
| Line 107... | Line 108... | ||
| 107 | { |
108 | { |
| 108 | pte_t *p = &pt[i]; |
109 | pte_t *p = &pt[i]; |
| 109 | 110 | ||
| 110 | p->c = (flags & PAGE_CACHEABLE) != 0 ? PAGE_CACHEABLE_EXC_WRITE : PAGE_UNCACHED; |
111 | p->c = (flags & PAGE_CACHEABLE) != 0 ? PAGE_CACHEABLE_EXC_WRITE : PAGE_UNCACHED; |
| 111 | p->v = !(flags & PAGE_NOT_PRESENT); |
112 | p->v = !(flags & PAGE_NOT_PRESENT); |
| 112 | p->d = (flags & PAGE_WRITE) != 0; |
113 | p->w = (flags & PAGE_WRITE) != 0; |
| 113 | } |
114 | } |
| 114 | 115 | ||
| 115 | extern void page_arch_init(void); |
116 | extern void page_arch_init(void); |
| 116 | 117 | ||
| 117 | extern pte_t *PTL0; |
118 | extern pte_t *PTL0; |