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 */
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 */
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#ifndef __ia64_REGISTER_H__
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#ifndef __ia64_REGISTER_H__
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#define __ia64_REGISTER_H__
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#define __ia64_REGISTER_H__
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#ifndef __ASM__
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#include <arch/types.h>
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#endif
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#define CR_IVR_MASK 0xf
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#define CR_IVR_MASK 0xf
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#define PSR_IC_MASK 0x2000
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#define PSR_IC_MASK 0x2000
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#define PSR_I_MASK  0x4000
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#define PSR_I_MASK  0x4000
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#define PSR_PK_MASK 0x8000
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#define PSR_PK_MASK 0x8000
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#define PSR_IT_MASK 0x0000001000000000
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#define PSR_IT_MASK 0x0000001000000000
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#define PSR_CPL_SHIFT       32
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#define PSR_CPL_SHIFT       32
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#define PSR_CPL_MASK_SHIFTED    3
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#define PSR_CPL_MASK_SHIFTED    3
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#define PFM_MASK        (~0x3fffffffff)
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#define RSC_MODE_MASK   3
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#define RSC_PL_MASK 12
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/** Application registers. */
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/** Application registers. */
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#define AR_KR0      0
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#define AR_KR0      0
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#define AR_KR1      1
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#define AR_KR1      1
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#define AR_KR2      2
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#define AR_KR2      2
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#define AR_KR3      3
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#define AR_KR3      3
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#define CR_LRR0     80
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#define CR_LRR0     80
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#define CR_LRR1     81
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#define CR_LRR1     81
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/* CR82-CR127 reserved */
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/* CR82-CR127 reserved */
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#ifndef __ASM__
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#ifndef __ASM__
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#include <arch/types.h>
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/** Processor Status Register. */
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union psr {
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    __u64 value;
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    struct {
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        unsigned : 1;
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        unsigned be : 1;    /**< Big-Endian data accesses. */
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        unsigned up : 1;    /**< User Performance monitor enable. */
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        unsigned ac : 1;    /**< Alignment Check. */
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        unsigned mfl : 1;   /**< Lower floating-point register written. */
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        unsigned mfh : 1;   /**< Upper floating-point register written. */
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        unsigned : 7;
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        unsigned ic : 1;    /**< Interruption Collection. */
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        unsigned i : 1;     /**< Interrupt Bit. */
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        unsigned pk : 1;    /**< Protection Key enable. */
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        unsigned : 1;
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        unsigned dt : 1;    /**< Data address Translation. */
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        unsigned dfl : 1;   /**< Disabled Floating-point Low register set. */
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        unsigned dfh : 1;   /**< Disabled Floating-point High register set. */
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        unsigned sp : 1;    /**< Secure Performance monitors. */
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        unsigned pp : 1;    /**< Privileged Performance monitor enable. */
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        unsigned di : 1;    /**< Disable Instruction set transition. */
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        unsigned si : 1;    /**< Secure Interval timer. */
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        unsigned db : 1;    /**< Debug Breakpoint fault. */
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        unsigned lp : 1;    /**< Lower Privilege transfer trap. */
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        unsigned tb : 1;    /**< Taken Branch trap. */
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        unsigned rt : 1;    /**< Register Stack Translation. */
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        unsigned : 4;
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        unsigned cpl : 2;   /**< Current Privilege Level. */
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        unsigned is : 1;    /**< Instruction Set. */
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        unsigned mc : 1;    /**< Machine Check abort mask. */
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        unsigned it : 1;    /**< Instruction address Translation. */
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        unsigned id : 1;    /**< Instruction Debug fault disable. */
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        unsigned da : 1;    /**< Disable Data Access and Dirty-bit faults. */
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        unsigned dd : 1;    /**< Data Debug fault disable. */
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        unsigned ss : 1;    /**< Single Step enable. */
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        unsigned ri : 2;    /**< Restart Instruction. */
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        unsigned ed : 1;    /**< Exception Deferral. */
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        unsigned bn : 1;    /**< Register Bank. */
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        unsigned ia : 1;    /**< Disable Instruction Access-bit faults. */
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    } __attribute__ ((packed));
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};
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typedef union psr psr_t;
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/** Register Stack Configuration Register */
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union rsc {
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    __u64 value;
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    struct {
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        unsigned mode : 2;
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        unsigned pl : 2;    /**< Privilege Level. */
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        unsigned be : 1;    /**< Big-endian. */
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        unsigned : 11;
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        unsigned loadrs : 14;
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    } __attribute__ ((packed));
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};
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typedef union rsc rsc_t;
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/** External Interrupt Vector Register */
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/** External Interrupt Vector Register */
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union cr_ivr {
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union cr_ivr {
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    __u8  vector;
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    __u8  vector;
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    __u64 value;
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    __u64 value;
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};
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};