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36 | #define CR_IVR_MASK 0xf |
36 | #define CR_IVR_MASK 0xf |
37 | #define PSR_IC_MASK 0x2000 |
37 | #define PSR_IC_MASK 0x2000 |
38 | #define PSR_I_MASK 0x4000 |
38 | #define PSR_I_MASK 0x4000 |
39 | #define PSR_PK_MASK 0x8000 |
39 | #define PSR_PK_MASK 0x8000 |
40 | 40 | ||
- | 41 | #define PSR_DT_MASK (1<<17) |
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- | 42 | #define PSR_RT_MASK (1<<27) |
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- | 43 | #define PSR_IT_MASK 0x0000001000000000 |
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- | 44 | ||
- | 45 | ||
- | 46 | ||
41 | /** Application registers. */ |
47 | /** Application registers. */ |
42 | #define AR_KR0 0 |
48 | #define AR_KR0 0 |
43 | #define AR_KR1 1 |
49 | #define AR_KR1 1 |
44 | #define AR_KR2 2 |
50 | #define AR_KR2 2 |
45 | #define AR_KR3 3 |
51 | #define AR_KR3 3 |