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41 | 41 | ||
42 | #define FAMILY_ITANIUM 0x7 |
42 | #define FAMILY_ITANIUM 0x7 |
43 | #define FAMILY_ITANIUM2 0x1f |
43 | #define FAMILY_ITANIUM2 0x1f |
44 | 44 | ||
45 | struct cpu_arch { |
45 | struct cpu_arch { |
46 | __u64 cpuid0; |
46 | uint64_t cpuid0; |
47 | __u64 cpuid1; |
47 | uint64_t cpuid1; |
48 | cpuid3_t cpuid3; |
48 | cpuid3_t cpuid3; |
49 | }; |
49 | }; |
50 | 50 | ||
51 | /** Read CPUID register. |
51 | /** Read CPUID register. |
52 | * |
52 | * |
53 | * @param n CPUID register number. |
53 | * @param n CPUID register number. |
54 | * |
54 | * |
55 | * @return Value of CPUID[n] register. |
55 | * @return Value of CPUID[n] register. |
56 | */ |
56 | */ |
57 | static inline __u64 cpuid_read(int n) |
57 | static inline uint64_t cpuid_read(int n) |
58 | { |
58 | { |
59 | __u64 v; |
59 | uint64_t v; |
60 | 60 | ||
61 | __asm__ volatile ("mov %0 = cpuid[%1]\n" : "=r" (v) : "r" (n)); |
61 | __asm__ volatile ("mov %0 = cpuid[%1]\n" : "=r" (v) : "r" (n)); |
62 | 62 | ||
63 | return v; |
63 | return v; |
64 | } |
64 | } |