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| Rev 576 | Rev 672 | ||
|---|---|---|---|
| Line 41... | Line 41... | ||
| 41 | #ifdef CONFIG_SMP |
41 | #ifdef CONFIG_SMP |
| 42 | 42 | ||
| 43 | /* |
43 | /* |
| 44 | * Advanced Programmable Interrupt Controller for SMP systems. |
44 | * Advanced Programmable Interrupt Controller for SMP systems. |
| 45 | * Tested on: |
45 | * Tested on: |
| 46 | * Bochs 2.0.2 - Bochs 2.2 with 2-8 CPUs |
46 | * Bochs 2.0.2 - Bochs 2.2.5 with 2-8 CPUs |
| 47 | * Simics 2.0.28 - Simics 2.2.19 2-15 CPUs |
47 | * Simics 2.0.28 - Simics 2.2.19 2-15 CPUs |
| 48 | * VMware Workstation 5.5 with 2 CPUs |
48 | * VMware Workstation 5.5 with 2 CPUs |
| 49 | * ASUS P/I-P65UP5 + ASUS C-P55T2D REV. 1.41 with 2x 200Mhz Pentium CPUs |
49 | * ASUS P/I-P65UP5 + ASUS C-P55T2D REV. 1.41 with 2x 200Mhz Pentium CPUs |
| 50 | * ASUS PCH-DL with 2x 3000Mhz Pentium 4 Xeon (HT) CPUs |
50 | * ASUS PCH-DL with 2x 3000Mhz Pentium 4 Xeon (HT) CPUs |
| 51 | * MSI K7D Master-L with 2x 2100MHz Athlon MP CPUs |
51 | * MSI K7D Master-L with 2x 2100MHz Athlon MP CPUs |
| Line 309... | Line 309... | ||
| 309 | lvt_lint_t lint; |
309 | lvt_lint_t lint; |
| 310 | svr_t svr; |
310 | svr_t svr; |
| 311 | icr_t icr; |
311 | icr_t icr; |
| 312 | tdcr_t tdcr; |
312 | tdcr_t tdcr; |
| 313 | lvt_tm_t tm; |
313 | lvt_tm_t tm; |
| - | 314 | ldr_t ldr; |
|
| - | 315 | dfr_t dfr; |
|
| 314 | __u32 t1, t2; |
316 | __u32 t1, t2; |
| 315 | 317 | ||
| 316 | /* Initialize LVT Error register. */ |
318 | /* Initialize LVT Error register. */ |
| 317 | error.value = l_apic[LVT_Err]; |
319 | error.value = l_apic[LVT_Err]; |
| 318 | error.masked = true; |
320 | error.masked = true; |
| Line 370... | Line 372... | ||
| 370 | t1 = l_apic[CCRT]; |
372 | t1 = l_apic[CCRT]; |
| 371 | delay(1000); |
373 | delay(1000); |
| 372 | t2 = l_apic[CCRT]; |
374 | t2 = l_apic[CCRT]; |
| 373 | 375 | ||
| 374 | l_apic[ICRT] = t1-t2; |
376 | l_apic[ICRT] = t1-t2; |
| - | 377 | ||
| - | 378 | /* Program Logical Destination Register. */ |
|
| - | 379 | ldr.value = l_apic[LDR]; |
|
| - | 380 | if (CPU->id < sizeof(CPU->id)*8) /* size in bits */ |
|
| - | 381 | ldr.id = (1<<CPU->id); |
|
| - | 382 | l_apic[LDR] = ldr.value; |
|
| - | 383 | ||
| - | 384 | /* Program Destination Format Register for Flat mode. */ |
|
| - | 385 | dfr.value = l_apic[DFR]; |
|
| - | 386 | dfr.model = MODEL_FLAT; |
|
| - | 387 | l_apic[DFR] = dfr.value; |
|
| 375 | } |
388 | } |
| 376 | 389 | ||
| 377 | /** Local APIC End of Interrupt. */ |
390 | /** Local APIC End of Interrupt. */ |
| 378 | void l_apic_eoi(void) |
391 | void l_apic_eoi(void) |
| 379 | { |
392 | { |
| Line 468... | Line 481... | ||
| 468 | int dlvr = DELMOD_FIXED; |
481 | int dlvr = DELMOD_FIXED; |
| 469 | 482 | ||
| 470 | if (flags & LOPRI) |
483 | if (flags & LOPRI) |
| 471 | dlvr = DELMOD_LOWPRI; |
484 | dlvr = DELMOD_LOWPRI; |
| 472 | 485 | ||
| 473 | - | ||
| 474 | reg.lo = io_apic_read(IOREDTBL + pin*2); |
486 | reg.lo = io_apic_read(IOREDTBL + pin*2); |
| 475 | reg.hi = io_apic_read(IOREDTBL + pin*2 + 1); |
487 | reg.hi = io_apic_read(IOREDTBL + pin*2 + 1); |
| 476 | 488 | ||
| 477 | reg.dest = dest; |
489 | reg.dest = dest; |
| 478 | reg.destmod = DESTMOD_LOGIC; |
490 | reg.destmod = DESTMOD_LOGIC; |
| 479 | reg.trigger_mode = TRIGMOD_EDGE; |
491 | reg.trigger_mode = TRIGMOD_EDGE; |
| 480 | reg.intpol = POLARITY_HIGH; |
492 | reg.intpol = POLARITY_HIGH; |
| 481 | reg.delmod = dlvr; |
493 | reg.delmod = dlvr; |
| 482 | reg.intvec = v; |
494 | reg.intvec = v; |