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| Rev 31 | Rev 34 | ||
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| Line 27... | Line 27... | ||
| 27 | */ |
27 | */ |
| 28 | 28 | ||
| 29 | #include <arch/types.h> |
29 | #include <arch/types.h> |
| 30 | #include <arch/smp/apic.h> |
30 | #include <arch/smp/apic.h> |
| 31 | #include <arch/smp/ap.h> |
31 | #include <arch/smp/ap.h> |
| 32 | #include <arch/smp/mp.h> |
32 | #include <arch/smp/mps.h> |
| 33 | #include <mm/page.h> |
33 | #include <mm/page.h> |
| 34 | #include <time/delay.h> |
34 | #include <time/delay.h> |
| 35 | #include <arch/interrupt.h> |
35 | #include <arch/interrupt.h> |
| 36 | #include <print.h> |
36 | #include <print.h> |
| 37 | #include <arch/asm.h> |
37 | #include <arch/asm.h> |
| Line 41... | Line 41... | ||
| 41 | 41 | ||
| 42 | /* |
42 | /* |
| 43 | * This is functional, far-from-general-enough interface to the APIC. |
43 | * This is functional, far-from-general-enough interface to the APIC. |
| 44 | * Advanced Programmable Interrupt Controller for MP systems. |
44 | * Advanced Programmable Interrupt Controller for MP systems. |
| 45 | * Tested on: |
45 | * Tested on: |
| 46 | * Bochs 2.0.2 with 2-8 CPUs |
46 | * Bochs 2.0.2 - Bochs 2.2-cvs with 2-8 CPUs |
| 47 | * ASUS P/I-P65UP5 + ASUS C-P55T2D REV. 1.41 with 2x 200Mhz Pentium CPUs |
47 | * ASUS P/I-P65UP5 + ASUS C-P55T2D REV. 1.41 with 2x 200Mhz Pentium CPUs |
| 48 | */ |
48 | */ |
| 49 | 49 | ||
| 50 | /* |
50 | /* |
| 51 | * These variables either stay configured as initilalized, or are changed by |
51 | * These variables either stay configured as initilalized, or are changed by |
| Line 80... | Line 80... | ||
| 80 | io_apic_disable_irqs(0xffff); |
80 | io_apic_disable_irqs(0xffff); |
| 81 | trap_register(VECTOR_CLK, l_apic_timer_interrupt); |
81 | trap_register(VECTOR_CLK, l_apic_timer_interrupt); |
| 82 | for (i=1; i<16; i++) { |
82 | for (i=1; i<16; i++) { |
| 83 | int pin; |
83 | int pin; |
| 84 | 84 | ||
| 85 | if ((pin = mp_irq_to_pin(i)) != -1) |
85 | if ((pin = mps_irq_to_pin(i)) != -1) |
| 86 | io_apic_change_ioredtbl(pin,0xf,IVT_IRQBASE+i,LOPRI); |
86 | io_apic_change_ioredtbl(pin,0xf,IVT_IRQBASE+i,LOPRI); |
| 87 | } |
87 | } |
| 88 | 88 | ||
| 89 | 89 | ||
| 90 | /* |
90 | /* |
| Line 377... | Line 377... | ||
| 377 | if ((irqmask>>i) & 1) { |
377 | if ((irqmask>>i) & 1) { |
| 378 | /* |
378 | /* |
| 379 | * Mask the signal input in IO APIC if there is a |
379 | * Mask the signal input in IO APIC if there is a |
| 380 | * mapping for the respective IRQ number. |
380 | * mapping for the respective IRQ number. |
| 381 | */ |
381 | */ |
| 382 | pin = mp_irq_to_pin(i); |
382 | pin = mps_irq_to_pin(i); |
| 383 | if (pin != -1) { |
383 | if (pin != -1) { |
| 384 | reglo = io_apic_read(IOREDTBL + pin*2); |
384 | reglo = io_apic_read(IOREDTBL + pin*2); |
| 385 | reglo |= (1<<16); |
385 | reglo |= (1<<16); |
| 386 | io_apic_write(IOREDTBL + pin*2,reglo); |
386 | io_apic_write(IOREDTBL + pin*2,reglo); |
| 387 | } |
387 | } |
| Line 399... | Line 399... | ||
| 399 | if ((irqmask>>i) & 1) { |
399 | if ((irqmask>>i) & 1) { |
| 400 | /* |
400 | /* |
| 401 | * Unmask the signal input in IO APIC if there is a |
401 | * Unmask the signal input in IO APIC if there is a |
| 402 | * mapping for the respective IRQ number. |
402 | * mapping for the respective IRQ number. |
| 403 | */ |
403 | */ |
| 404 | pin = mp_irq_to_pin(i); |
404 | pin = mps_irq_to_pin(i); |
| 405 | if (pin != -1) { |
405 | if (pin != -1) { |
| 406 | reglo = io_apic_read(IOREDTBL + pin*2); |
406 | reglo = io_apic_read(IOREDTBL + pin*2); |
| 407 | reglo &= ~(1<<16); |
407 | reglo &= ~(1<<16); |
| 408 | io_apic_write(IOREDTBL + pin*2,reglo); |
408 | io_apic_write(IOREDTBL + pin*2,reglo); |
| 409 | } |
409 | } |