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 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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 */
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 */
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#ifdef __SMP__
 - 
 
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 - 
 
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#include <arch/types.h>
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#include <arch/types.h>
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#include <arch/smp/apic.h>
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#include <arch/smp/apic.h>
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#include <arch/smp/ap.h>
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#include <arch/smp/ap.h>
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#include <arch/smp/mp.h>
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#include <arch/smp/mp.h>
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#include <mm/page.h>
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#include <mm/page.h>
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#include <arch/interrupt.h>
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#include <arch/interrupt.h>
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#include <print.h>
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#include <print.h>
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#include <arch/asm.h>
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#include <arch/asm.h>
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#include <arch.h>
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#include <arch.h>
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#ifdef __SMP__
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/*
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/*
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 * This is functional, far-from-general-enough interface to the APIC.
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 * This is functional, far-from-general-enough interface to the APIC.
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 * Advanced Programmable Interrupt Controller for MP systems.
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 * Advanced Programmable Interrupt Controller for MP systems.
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 * Tested on:
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 * Tested on:
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 *  Bochs 2.0.2 with 2-8 CPUs
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 *  Bochs 2.0.2 with 2-8 CPUs
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}
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}
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void l_apic_init(void)
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void l_apic_init(void)
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{
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{
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    __u32 tmp, t1, t2;
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    __u32 tmp, t1, t2;
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    int cpu_id = config.cpu_active - 1;
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    /*
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     * Here we set local APIC ID's so that they match operating system's CPU ID's
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     * This operation is dangerous as it is model specific.
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     * TODO: some care should be taken.
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     * NOTE: CPU may not be used to define APIC ID
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     */
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    if (l_apic_id() != cpu_id) {
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        l_apic[L_APIC_ID] &= L_APIC_IDClear;
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        l_apic[L_APIC_ID] |= (l_apic[L_APIC_ID]&L_APIC_IDClear)|((cpu_id)<<L_APIC_IDShift);
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    }
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    l_apic[LVT_Err] |= (1<<16);
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    l_apic[LVT_Err] |= (1<<16);
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    l_apic[LVT_LINT0] |= (1<<16);
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    l_apic[LVT_LINT0] |= (1<<16);
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    l_apic[LVT_LINT1] |= (1<<16);
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    l_apic[LVT_LINT1] |= (1<<16);
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    tmp = l_apic[SVR] & SVRClear;
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    tmp = l_apic[SVR] & SVRClear;
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void l_apic_debug(void)
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void l_apic_debug(void)
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{
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{
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#ifdef LAPIC_VERBOSE
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#ifdef LAPIC_VERBOSE
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    int i, lint;
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    int i, lint;
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    printf("LVT on cpu%d, LAPIC ID: %d\n", CPU->id, (l_apic[L_APIC_ID] >> 24)&0xf);
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    printf("LVT on cpu%d, LAPIC ID: %d\n", CPU->id, l_apic_id());
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    printf("LVT_Tm: ");
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    printf("LVT_Tm: ");
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    if (l_apic[LVT_Tm] & (1<<17)) printf("periodic"); else printf("one-shot"); putchar(',');   
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    if (l_apic[LVT_Tm] & (1<<17)) printf("periodic"); else printf("one-shot"); putchar(',');   
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    if (l_apic[LVT_Tm] & (1<<16)) printf("masked"); else printf("not masked"); putchar(',');
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    if (l_apic[LVT_Tm] & (1<<16)) printf("masked"); else printf("not masked"); putchar(',');
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    if (l_apic[LVT_Tm] & (1<<12)) printf("send pending"); else printf("idle"); putchar(',');
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    if (l_apic[LVT_Tm] & (1<<12)) printf("send pending"); else printf("idle"); putchar(',');
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    printf("%B\n", l_apic[LVT_Err] & 0xff);
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    printf("%B\n", l_apic[LVT_Err] & 0xff);
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 315 
 
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    /*
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    /*
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     * This register is supported only on P6 and higher.
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     * This register is supported only on P6 and higher.
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     */
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     */
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    if (CPU->family > 5) {
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    if (CPU->arch.family > 5) {
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        printf("LVT_PCINT: ");
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        printf("LVT_PCINT: ");
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        if (l_apic[LVT_PCINT] & (1<<16)) printf("masked"); else printf("not masked"); putchar(',');
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        if (l_apic[LVT_PCINT] & (1<<16)) printf("masked"); else printf("not masked"); putchar(',');
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        if (l_apic[LVT_PCINT] & (1<<12)) printf("send pending"); else printf("idle"); putchar(',');
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        if (l_apic[LVT_PCINT] & (1<<12)) printf("send pending"); else printf("idle"); putchar(',');
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        switch ((l_apic[LVT_PCINT] >> 8)&7) {
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        switch ((l_apic[LVT_PCINT] >> 8)&7) {
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            case 0: printf("fixed"); break;
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            case 0: printf("fixed"); break;
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{
 335 
{
324 
    l_apic_eoi();
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    l_apic_eoi();
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    clock();
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    clock();
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}
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}
327 
 
 339 
 
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 340 
__u8 l_apic_id(void)
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 341 
{
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 342 
    return (l_apic[L_APIC_ID] >> L_APIC_IDShift)&L_APIC_IDMask;
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 343 
}
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 344 
 
328 
__u32 io_apic_read(__u8 address)
 345 
__u32 io_apic_read(__u8 address)
329 
{
 346 
{
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    __u32 tmp;
 347 
    __u32 tmp;
331 
   
 348 
   
332 
    tmp = io_apic[IOREGSEL] & ~0xf;
 349 
    tmp = io_apic[IOREGSEL] & ~0xf;