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        ASSERT(TASK->arch.iomap.map);
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        ASSERT(TASK->arch.iomap.map);
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        bitmap_initialize(&iomap, CPU->arch.tss->iomap, TSS_IOMAP_SIZE * 8);
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        bitmap_initialize(&iomap, CPU->arch.tss->iomap, TSS_IOMAP_SIZE * 8);
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        bitmap_copy(&iomap, &TASK->arch.iomap, TASK->arch.iomap.bits);
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        bitmap_copy(&iomap, &TASK->arch.iomap, TASK->arch.iomap.bits);
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        /*
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        /*
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         * It is safe to set the trailing four bits because of the extra
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         * It is safe to set the trailing eight bits because of the extra
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         * convenience byte in TSS_IOMAP_SIZE.
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         * convenience byte in TSS_IOMAP_SIZE.
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         */
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         */
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        bitmap_set_range(&iomap, TASK->arch.iomap.bits, 4);
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        bitmap_set_range(&iomap, TASK->arch.iomap.bits, 8);
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    }
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    }
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    spinlock_unlock(&TASK->lock);
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    spinlock_unlock(&TASK->lock);
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    /* Second, adjust TSS segment limit. */
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    /* Second, adjust TSS segment limit. */
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    gdtr_store(&cpugdtr);
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    gdtr_store(&cpugdtr);
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    gdt_p = (descriptor_t *) cpugdtr.base;
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    gdt_p = (descriptor_t *) cpugdtr.base;
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    gdt_setlimit(&gdt_p[TSS_DES], TSS_BASIC_SIZE + BITS2BYTES(bits) - 1);
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    gdt_setlimit(&gdt_p[TSS_DES], TSS_BASIC_SIZE + BITS2BYTES(bits) - 1);
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    gdtr_load(&cpugdtr);
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    gdtr_load(&cpugdtr);
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    /*
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     * Before we load new TSS limit, the current TSS descriptor
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     * type must be changed to describe inactive TSS.
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     */
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    gdt_p[TSS_DES].access = AR_PRESENT | AR_TSS | DPL_KERNEL;
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    tr_load(selector(TSS_DES));
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}
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}
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/** Perform ia32 specific tasks needed before the new thread is scheduled.
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/** Perform ia32 specific tasks needed before the new thread is scheduled.
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 *
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 *
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 * THREAD is locked and interrupts are disabled.
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 * THREAD is locked and interrupts are disabled.