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- | 1 | /* |
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- | 2 | * Copyright (C) 2001-2004 Jakub Jermar |
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- | 3 | * All rights reserved. |
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- | 4 | * |
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- | 5 | * Redistribution and use in source and binary forms, with or without |
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- | 6 | * modification, are permitted provided that the following conditions |
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- | 7 | * are met: |
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- | 8 | * |
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- | 9 | * - Redistributions of source code must retain the above copyright |
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- | 10 | * notice, this list of conditions and the following disclaimer. |
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- | 11 | * - Redistributions in binary form must reproduce the above copyright |
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- | 12 | * notice, this list of conditions and the following disclaimer in the |
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- | 13 | * documentation and/or other materials provided with the distribution. |
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- | 14 | * - The name of the author may not be used to endorse or promote products |
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- | 15 | * derived from this software without specific prior written permission. |
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- | 16 | * |
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- | 17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
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- | 18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
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- | 19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
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- | 20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
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- | 21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
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- | 22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
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- | 23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
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- | 24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
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- | 25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
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- | 26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
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- | 27 | */ |
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- | 28 | ||
- | 29 | #include <arch/pm.h> |
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- | 30 | #include <config.h> |
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- | 31 | #include <arch/types.h> |
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- | 32 | #include <typedefs.h> |
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- | 33 | #include <arch/interrupt.h> |
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- | 34 | #include <arch/asm.h> |
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- | 35 | #include <arch/context.h> |
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- | 36 | #include <panic.h> |
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- | 37 | #include <arch/mm/page.h> |
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- | 38 | #include <mm/heap.h> |
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- | 39 | #include <memstr.h> |
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- | 40 | #include <arch/boot/boot.h> |
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- | 41 | ||
- | 42 | /* |
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- | 43 | * Early ia32 configuration functions and data structures. |
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- | 44 | */ |
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- | 45 | ||
- | 46 | /* |
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- | 47 | * We have no use for segmentation so we set up flat mode. In this |
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- | 48 | * mode, we use, for each privilege level, two segments spanning the |
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- | 49 | * whole memory. One is for code and one is for data. |
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- | 50 | */ |
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- | 51 | struct descriptor gdt[GDT_ITEMS] = { |
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- | 52 | /* NULL descriptor */ |
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- | 53 | { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, |
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- | 54 | /* KTEXT descriptor */ |
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- | 55 | { 0xffff, 0, 0, AR_PRESENT | AR_CODE | DPL_KERNEL, 0xf, 0, 0, 1, 1, 0 }, |
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- | 56 | /* KDATA descriptor */ |
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- | 57 | { 0xffff, 0, 0, AR_PRESENT | AR_DATA | AR_WRITABLE | DPL_KERNEL, 0xf, 0, 0, 1, 1, 0 }, |
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- | 58 | /* UTEXT descriptor */ |
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- | 59 | { 0xffff, 0, 0, AR_PRESENT | AR_CODE | DPL_USER, 0xf, 0, 0, 1, 1, 0 }, |
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- | 60 | /* UDATA descriptor */ |
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- | 61 | { 0xffff, 0, 0, AR_PRESENT | AR_DATA | AR_WRITABLE | DPL_USER, 0xf, 0, 0, 1, 1, 0 }, |
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- | 62 | /* TSS descriptor - set up will be completed later */ |
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- | 63 | { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } |
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- | 64 | }; |
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- | 65 | ||
- | 66 | static struct idescriptor idt[IDT_ITEMS]; |
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- | 67 | ||
- | 68 | static struct tss tss; |
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- | 69 | ||
- | 70 | struct tss *tss_p = NULL; |
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- | 71 | ||
- | 72 | /* gdtr is changed by kmp before next CPU is initialized */ |
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- | 73 | struct ptr_16_32 protected_bootstrap_gdtr = { .limit = sizeof(gdt), .base = KA2PA((__address) gdt) }; |
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- | 74 | struct ptr_16_32 gdtr = { .limit = sizeof(gdt), .base = (__address) gdt }; |
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- | 75 | ||
- | 76 | void gdt_setbase(struct descriptor *d, __address base) |
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- | 77 | { |
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- | 78 | d->base_0_15 = base & 0xffff; |
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- | 79 | d->base_16_23 = ((base) >> 16) & 0xff; |
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- | 80 | d->base_24_31 = ((base) >> 24) & 0xff; |
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- | 81 | } |
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- | 82 | ||
- | 83 | void gdt_setlimit(struct descriptor *d, __u32 limit) |
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- | 84 | { |
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- | 85 | d->limit_0_15 = limit & 0xffff; |
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- | 86 | d->limit_16_19 = (limit >> 16) & 0xf; |
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- | 87 | } |
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- | 88 | ||
- | 89 | void idt_setoffset(struct idescriptor *d, __address offset) |
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- | 90 | { |
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- | 91 | /* |
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- | 92 | * Offset is a linear address. |
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- | 93 | */ |
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- | 94 | d->offset_0_15 = offset & 0xffff; |
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- | 95 | d->offset_16_31 = offset >> 16; |
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- | 96 | } |
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- | 97 | ||
- | 98 | void tss_initialize(struct tss *t) |
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- | 99 | { |
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- | 100 | memsetb((__address) t, sizeof(struct tss), 0); |
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- | 101 | } |
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- | 102 | ||
- | 103 | /* |
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- | 104 | * This function takes care of proper setup of IDT and IDTR. |
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- | 105 | */ |
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- | 106 | void idt_init(void) |
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- | 107 | { |
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- | 108 | struct idescriptor *d; |
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- | 109 | int i; |
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- | 110 | ||
- | 111 | for (i = 0; i < IDT_ITEMS; i++) { |
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- | 112 | d = &idt[i]; |
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- | 113 | ||
- | 114 | d->unused = 0; |
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- | 115 | d->selector = selector(KTEXT_DES); |
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- | 116 | ||
- | 117 | d->access = AR_PRESENT | AR_INTERRUPT; /* masking interrupt */ |
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- | 118 | ||
- | 119 | if (i == VECTOR_SYSCALL) { |
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- | 120 | /* |
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- | 121 | * The syscall interrupt gate must be calleable from userland. |
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- | 122 | */ |
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- | 123 | d->access |= DPL_USER; |
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- | 124 | } |
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- | 125 | ||
- | 126 | idt_setoffset(d, ((__address) interrupt_handlers) + i*interrupt_handler_size); |
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- | 127 | trap_register(i, null_interrupt); |
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- | 128 | } |
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- | 129 | trap_register(13, gp_fault); |
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- | 130 | trap_register( 7, nm_fault); |
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- | 131 | trap_register(12, ss_fault); |
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- | 132 | } |
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- | 133 | ||
- | 134 | ||
- | 135 | /* Clean IOPL(12,13) and NT(14) flags in EFLAGS register */ |
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- | 136 | static void clean_IOPL_NT_flags(void) |
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- | 137 | { |
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- | 138 | asm |
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- | 139 | ( |
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- | 140 | "pushfl;" |
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- | 141 | "pop %%eax;" |
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- | 142 | "and $0xffff8fff,%%eax;" |
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- | 143 | "push %%eax;" |
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- | 144 | "popfl;" |
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- | 145 | : |
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- | 146 | : |
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- | 147 | :"%eax" |
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- | 148 | ); |
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- | 149 | } |
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- | 150 | ||
- | 151 | /* Clean AM(18) flag in CR0 register */ |
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- | 152 | static void clean_AM_flag(void) |
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- | 153 | { |
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- | 154 | asm |
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- | 155 | ( |
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- | 156 | "mov %%cr0,%%eax;" |
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- | 157 | "and $0xFFFBFFFF,%%eax;" |
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- | 158 | "mov %%eax,%%cr0;" |
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- | 159 | : |
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- | 160 | : |
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- | 161 | :"%eax" |
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- | 162 | ); |
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- | 163 | } |
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- | 164 | ||
- | 165 | void pm_init(void) |
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- | 166 | { |
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- | 167 | struct descriptor *gdt_p = (struct descriptor *) gdtr.base; |
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- | 168 | struct ptr_16_32 idtr; |
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- | 169 | ||
- | 170 | /* |
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- | 171 | * Update addresses in GDT and IDT to their virtual counterparts. |
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- | 172 | */ |
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- | 173 | idtr.limit = sizeof(idt); |
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- | 174 | idtr.base = (__address) idt; |
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- | 175 | __asm__ volatile ("lgdt %0\n" : : "m" (gdtr)); |
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- | 176 | __asm__ volatile ("lidt %0\n" : : "m" (idtr)); |
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- | 177 | ||
- | 178 | /* |
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- | 179 | * Each CPU has its private GDT and TSS. |
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- | 180 | * All CPUs share one IDT. |
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- | 181 | */ |
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- | 182 | ||
- | 183 | if (config.cpu_active == 1) { |
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- | 184 | idt_init(); |
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- | 185 | /* |
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- | 186 | * NOTE: bootstrap CPU has statically allocated TSS, because |
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- | 187 | * the heap hasn't been initialized so far. |
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- | 188 | */ |
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- | 189 | tss_p = &tss; |
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- | 190 | } |
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- | 191 | else { |
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- | 192 | tss_p = (struct tss *) malloc(sizeof(struct tss)); |
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- | 193 | if (!tss_p) |
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- | 194 | panic("could not allocate TSS\n"); |
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- | 195 | } |
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- | 196 | ||
- | 197 | tss_initialize(tss_p); |
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- | 198 | ||
- | 199 | gdt_p[TSS_DES].access = AR_PRESENT | AR_TSS | DPL_KERNEL; |
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- | 200 | gdt_p[TSS_DES].special = 1; |
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- | 201 | gdt_p[TSS_DES].granularity = 1; |
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- | 202 | ||
- | 203 | gdt_setbase(&gdt_p[TSS_DES], (__address) tss_p); |
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- | 204 | gdt_setlimit(&gdt_p[TSS_DES], sizeof(struct tss) - 1); |
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- | 205 | ||
- | 206 | /* |
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- | 207 | * As of this moment, the current CPU has its own GDT pointing |
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- | 208 | * to its own TSS. We just need to load the TR register. |
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- | 209 | */ |
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- | 210 | __asm__ volatile ("ltr %0" : : "r" ((__u16) selector(TSS_DES))); |
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- | 211 | ||
- | 212 | clean_IOPL_NT_flags(); /* Disable I/O on nonprivileged levels */ |
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- | 213 | clean_AM_flag(); /* Disable alignment check */ |
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- | 214 | } |