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- | 1 | /* |
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- | 2 | * Copyright (C) 2001-2004 Jakub Jermar |
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- | 3 | * Copyright (C) 2005 Sergey Bondari |
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- | 4 | * All rights reserved. |
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- | 5 | * |
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- | 6 | * Redistribution and use in source and binary forms, with or without |
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- | 7 | * modification, are permitted provided that the following conditions |
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- | 8 | * are met: |
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- | 9 | * |
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- | 10 | * - Redistributions of source code must retain the above copyright |
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- | 11 | * notice, this list of conditions and the following disclaimer. |
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- | 12 | * - Redistributions in binary form must reproduce the above copyright |
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- | 13 | * notice, this list of conditions and the following disclaimer in the |
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- | 14 | * documentation and/or other materials provided with the distribution. |
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- | 15 | * - The name of the author may not be used to endorse or promote products |
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- | 16 | * derived from this software without specific prior written permission. |
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- | 17 | * |
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- | 18 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
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- | 19 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
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- | 20 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
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- | 21 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
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- | 22 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
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- | 23 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
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- | 24 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
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- | 25 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
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- | 26 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
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- | 27 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
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- | 28 | */ |
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- | 29 | ||
- | 30 | #ifndef __ia32_ASM_H__ |
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- | 31 | #define __ia32_ASM_H__ |
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- | 32 | ||
- | 33 | #include <arch/types.h> |
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- | 34 | #include <config.h> |
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- | 35 | ||
- | 36 | extern __u32 interrupt_handler_size; |
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- | 37 | ||
- | 38 | extern void paging_on(void); |
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- | 39 | ||
- | 40 | extern void interrupt_handlers(void); |
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- | 41 | ||
- | 42 | extern void enable_l_apic_in_msr(void); |
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- | 43 | ||
- | 44 | ||
- | 45 | void asm_delay_loop(__u32 t); |
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- | 46 | void asm_fake_loop(__u32 t); |
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- | 47 | ||
- | 48 | ||
- | 49 | /** Halt CPU |
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- | 50 | * |
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- | 51 | * Halt the current CPU until interrupt event. |
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- | 52 | */ |
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- | 53 | static inline void cpu_halt(void) { __asm__("hlt\n"); }; |
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- | 54 | static inline void cpu_sleep(void) { __asm__("hlt\n"); }; |
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- | 55 | ||
- | 56 | /** Read CR2 |
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- | 57 | * |
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- | 58 | * Return value in CR2 |
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- | 59 | * |
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- | 60 | * @return Value read. |
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- | 61 | */ |
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- | 62 | static inline __u32 read_cr2(void) { __u32 v; __asm__ volatile ("movl %%cr2,%0\n" : "=r" (v)); return v; } |
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- | 63 | ||
- | 64 | /** Write CR3 |
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- | 65 | * |
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- | 66 | * Write value to CR3. |
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- | 67 | * |
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- | 68 | * @param v Value to be written. |
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- | 69 | */ |
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- | 70 | static inline void write_cr3(__u32 v) { __asm__ volatile ("movl %0,%%cr3\n" : : "r" (v)); } |
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- | 71 | ||
- | 72 | /** Read CR3 |
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- | 73 | * |
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- | 74 | * Return value in CR3 |
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- | 75 | * |
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- | 76 | * @return Value read. |
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- | 77 | */ |
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- | 78 | static inline __u32 read_cr3(void) { __u32 v; __asm__ volatile ("movl %%cr3,%0\n" : "=r" (v)); return v; } |
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- | 79 | ||
- | 80 | /** Byte to port |
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- | 81 | * |
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- | 82 | * Output byte to port |
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- | 83 | * |
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- | 84 | * @param port Port to write to |
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- | 85 | * @param val Value to write |
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- | 86 | */ |
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- | 87 | static inline void outb(__u16 port, __u8 val) { __asm__ volatile ("outb %b0, %w1\n" : : "a" (val), "d" (port) ); } |
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- | 88 | ||
- | 89 | /** Word to port |
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- | 90 | * |
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- | 91 | * Output word to port |
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- | 92 | * |
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- | 93 | * @param port Port to write to |
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- | 94 | * @param val Value to write |
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- | 95 | */ |
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- | 96 | static inline void outw(__u16 port, __u16 val) { __asm__ volatile ("outw %w0, %w1\n" : : "a" (val), "d" (port) ); } |
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- | 97 | ||
- | 98 | /** Double word to port |
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- | 99 | * |
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- | 100 | * Output double word to port |
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- | 101 | * |
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- | 102 | * @param port Port to write to |
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- | 103 | * @param val Value to write |
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- | 104 | */ |
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- | 105 | static inline void outl(__u16 port, __u32 val) { __asm__ volatile ("outl %l0, %w1\n" : : "a" (val), "d" (port) ); } |
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- | 106 | ||
- | 107 | /** Byte from port |
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- | 108 | * |
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- | 109 | * Get byte from port |
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- | 110 | * |
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- | 111 | * @param port Port to read from |
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- | 112 | * @return Value read |
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- | 113 | */ |
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- | 114 | static inline __u8 inb(__u16 port) { __u8 val; __asm__ volatile ("inb %w1, %b0 \n" : "=a" (val) : "d" (port) ); return val; } |
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- | 115 | ||
- | 116 | /** Word from port |
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- | 117 | * |
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- | 118 | * Get word from port |
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- | 119 | * |
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- | 120 | * @param port Port to read from |
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- | 121 | * @return Value read |
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- | 122 | */ |
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- | 123 | static inline __u16 inw(__u16 port) { __u16 val; __asm__ volatile ("inw %w1, %w0 \n" : "=a" (val) : "d" (port) ); return val; } |
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- | 124 | ||
- | 125 | /** Double word from port |
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- | 126 | * |
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- | 127 | * Get double word from port |
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- | 128 | * |
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- | 129 | * @param port Port to read from |
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- | 130 | * @return Value read |
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- | 131 | */ |
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- | 132 | static inline __u32 inl(__u16 port) { __u32 val; __asm__ volatile ("inl %w1, %l0 \n" : "=a" (val) : "d" (port) ); return val; } |
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- | 133 | ||
- | 134 | /** Enable interrupts. |
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- | 135 | * |
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- | 136 | * Enable interrupts and return previous |
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- | 137 | * value of EFLAGS. |
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- | 138 | * |
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- | 139 | * @return Old interrupt priority level. |
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- | 140 | */ |
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- | 141 | static inline ipl_t interrupts_enable(void) |
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- | 142 | { |
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- | 143 | ipl_t v; |
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- | 144 | __asm__ volatile ( |
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- | 145 | "pushf\n\t" |
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- | 146 | "popl %0\n\t" |
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- | 147 | "sti\n" |
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- | 148 | : "=r" (v) |
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- | 149 | ); |
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- | 150 | return v; |
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- | 151 | } |
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- | 152 | ||
- | 153 | /** Disable interrupts. |
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- | 154 | * |
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- | 155 | * Disable interrupts and return previous |
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- | 156 | * value of EFLAGS. |
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- | 157 | * |
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- | 158 | * @return Old interrupt priority level. |
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- | 159 | */ |
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- | 160 | static inline ipl_t interrupts_disable(void) |
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- | 161 | { |
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- | 162 | ipl_t v; |
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- | 163 | __asm__ volatile ( |
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- | 164 | "pushf\n\t" |
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- | 165 | "popl %0\n\t" |
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- | 166 | "cli\n" |
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- | 167 | : "=r" (v) |
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- | 168 | ); |
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- | 169 | return v; |
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- | 170 | } |
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- | 171 | ||
- | 172 | /** Restore interrupt priority level. |
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- | 173 | * |
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- | 174 | * Restore EFLAGS. |
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- | 175 | * |
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- | 176 | * @param ipl Saved interrupt priority level. |
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- | 177 | */ |
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- | 178 | static inline void interrupts_restore(ipl_t ipl) |
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- | 179 | { |
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- | 180 | __asm__ volatile ( |
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- | 181 | "pushl %0\n\t" |
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- | 182 | "popf\n" |
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- | 183 | : : "r" (ipl) |
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- | 184 | ); |
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- | 185 | } |
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- | 186 | ||
- | 187 | /** Return interrupt priority level. |
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- | 188 | * |
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- | 189 | * @return EFLAFS. |
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- | 190 | */ |
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- | 191 | static inline ipl_t interrupts_read(void) |
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- | 192 | { |
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- | 193 | ipl_t v; |
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- | 194 | __asm__ volatile ( |
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- | 195 | "pushf\n\t" |
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- | 196 | "popl %0\n" |
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- | 197 | : "=r" (v) |
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- | 198 | ); |
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- | 199 | return v; |
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- | 200 | } |
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- | 201 | ||
- | 202 | /** Return base address of current stack |
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- | 203 | * |
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- | 204 | * Return the base address of the current stack. |
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- | 205 | * The stack is assumed to be STACK_SIZE bytes long. |
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- | 206 | * The stack must start on page boundary. |
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- | 207 | */ |
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- | 208 | static inline __address get_stack_base(void) |
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- | 209 | { |
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- | 210 | __address v; |
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- | 211 | ||
- | 212 | __asm__ volatile ("andl %%esp, %0\n" : "=r" (v) : "0" (~(STACK_SIZE-1))); |
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- | 213 | ||
- | 214 | return v; |
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- | 215 | } |
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- | 216 | ||
- | 217 | static inline __u64 rdtsc(void) |
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- | 218 | { |
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- | 219 | __u64 v; |
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- | 220 | ||
- | 221 | __asm__ volatile("rdtsc\n" : "=A" (v)); |
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- | 222 | ||
- | 223 | return v; |
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- | 224 | } |
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- | 225 | ||
- | 226 | #endif |