Rev 1702 | Show entire file | Ignore whitespace | Details | Blame | Last modification | View Log | RSS feed
| Rev 1702 | Rev 1780 | ||
|---|---|---|---|
| Line 121... | Line 121... | ||
| 121 | #endif |
121 | #endif |
| 122 | }; |
122 | }; |
| 123 | 123 | ||
| 124 | idescriptor_t idt[IDT_ITEMS]; |
124 | idescriptor_t idt[IDT_ITEMS]; |
| 125 | 125 | ||
| 126 | ptr_16_64_t gdtr = {.limit = sizeof(gdt), .base= (__u64) gdt }; |
126 | ptr_16_64_t gdtr = {.limit = sizeof(gdt), .base= (uint64_t) gdt }; |
| 127 | ptr_16_64_t idtr = {.limit = sizeof(idt), .base= (__u64) idt }; |
127 | ptr_16_64_t idtr = {.limit = sizeof(idt), .base= (uint64_t) idt }; |
| 128 | 128 | ||
| 129 | static tss_t tss; |
129 | static tss_t tss; |
| 130 | tss_t *tss_p = NULL; |
130 | tss_t *tss_p = NULL; |
| 131 | 131 | ||
| 132 | void gdt_tss_setbase(descriptor_t *d, __address base) |
132 | void gdt_tss_setbase(descriptor_t *d, uintptr_t base) |
| 133 | { |
133 | { |
| 134 | tss_descriptor_t *td = (tss_descriptor_t *) d; |
134 | tss_descriptor_t *td = (tss_descriptor_t *) d; |
| 135 | 135 | ||
| 136 | td->base_0_15 = base & 0xffff; |
136 | td->base_0_15 = base & 0xffff; |
| 137 | td->base_16_23 = ((base) >> 16) & 0xff; |
137 | td->base_16_23 = ((base) >> 16) & 0xff; |
| 138 | td->base_24_31 = ((base) >> 24) & 0xff; |
138 | td->base_24_31 = ((base) >> 24) & 0xff; |
| 139 | td->base_32_63 = ((base) >> 32); |
139 | td->base_32_63 = ((base) >> 32); |
| 140 | } |
140 | } |
| 141 | 141 | ||
| 142 | void gdt_tss_setlimit(descriptor_t *d, __u32 limit) |
142 | void gdt_tss_setlimit(descriptor_t *d, uint32_t limit) |
| 143 | { |
143 | { |
| 144 | struct tss_descriptor *td = (tss_descriptor_t *) d; |
144 | struct tss_descriptor *td = (tss_descriptor_t *) d; |
| 145 | 145 | ||
| 146 | td->limit_0_15 = limit & 0xffff; |
146 | td->limit_0_15 = limit & 0xffff; |
| 147 | td->limit_16_19 = (limit >> 16) & 0xf; |
147 | td->limit_16_19 = (limit >> 16) & 0xf; |
| 148 | } |
148 | } |
| 149 | 149 | ||
| 150 | void idt_setoffset(idescriptor_t *d, __address offset) |
150 | void idt_setoffset(idescriptor_t *d, uintptr_t offset) |
| 151 | { |
151 | { |
| 152 | /* |
152 | /* |
| 153 | * Offset is a linear address. |
153 | * Offset is a linear address. |
| 154 | */ |
154 | */ |
| 155 | d->offset_0_15 = offset & 0xffff; |
155 | d->offset_0_15 = offset & 0xffff; |
| Line 157... | Line 157... | ||
| 157 | d->offset_32_63 = offset >> 32; |
157 | d->offset_32_63 = offset >> 32; |
| 158 | } |
158 | } |
| 159 | 159 | ||
| 160 | void tss_initialize(tss_t *t) |
160 | void tss_initialize(tss_t *t) |
| 161 | { |
161 | { |
| 162 | memsetb((__address) t, sizeof(tss_t), 0); |
162 | memsetb((uintptr_t) t, sizeof(tss_t), 0); |
| 163 | } |
163 | } |
| 164 | 164 | ||
| 165 | /* |
165 | /* |
| 166 | * This function takes care of proper setup of IDT and IDTR. |
166 | * This function takes care of proper setup of IDT and IDTR. |
| 167 | */ |
167 | */ |
| Line 177... | Line 177... | ||
| 177 | d->selector = gdtselector(KTEXT_DES); |
177 | d->selector = gdtselector(KTEXT_DES); |
| 178 | 178 | ||
| 179 | d->present = 1; |
179 | d->present = 1; |
| 180 | d->type = AR_INTERRUPT; /* masking interrupt */ |
180 | d->type = AR_INTERRUPT; /* masking interrupt */ |
| 181 | 181 | ||
| 182 | idt_setoffset(d, ((__address) interrupt_handlers) + i*interrupt_handler_size); |
182 | idt_setoffset(d, ((uintptr_t) interrupt_handlers) + i*interrupt_handler_size); |
| 183 | exc_register(i, "undef", (iroutine)null_interrupt); |
183 | exc_register(i, "undef", (iroutine)null_interrupt); |
| 184 | } |
184 | } |
| 185 | 185 | ||
| 186 | exc_register( 7, "nm_fault", nm_fault); |
186 | exc_register( 7, "nm_fault", nm_fault); |
| 187 | exc_register(12, "ss_fault", ss_fault); |
187 | exc_register(12, "ss_fault", ss_fault); |
| Line 212... | Line 212... | ||
| 212 | } |
212 | } |
| 213 | else { |
213 | else { |
| 214 | /* We are going to use malloc, which may return |
214 | /* We are going to use malloc, which may return |
| 215 | * non boot-mapped pointer, initialize the CR3 register |
215 | * non boot-mapped pointer, initialize the CR3 register |
| 216 | * ahead of page_init */ |
216 | * ahead of page_init */ |
| 217 | write_cr3((__address) AS_KERNEL->page_table); |
217 | write_cr3((uintptr_t) AS_KERNEL->page_table); |
| 218 | 218 | ||
| 219 | tss_p = (struct tss *) malloc(sizeof(tss_t), FRAME_ATOMIC); |
219 | tss_p = (struct tss *) malloc(sizeof(tss_t), FRAME_ATOMIC); |
| 220 | if (!tss_p) |
220 | if (!tss_p) |
| 221 | panic("could not allocate TSS\n"); |
221 | panic("could not allocate TSS\n"); |
| 222 | } |
222 | } |
| Line 226... | Line 226... | ||
| 226 | tss_desc = (tss_descriptor_t *) (&gdt_p[TSS_DES]); |
226 | tss_desc = (tss_descriptor_t *) (&gdt_p[TSS_DES]); |
| 227 | tss_desc->present = 1; |
227 | tss_desc->present = 1; |
| 228 | tss_desc->type = AR_TSS; |
228 | tss_desc->type = AR_TSS; |
| 229 | tss_desc->dpl = PL_KERNEL; |
229 | tss_desc->dpl = PL_KERNEL; |
| 230 | 230 | ||
| 231 | gdt_tss_setbase(&gdt_p[TSS_DES], (__address) tss_p); |
231 | gdt_tss_setbase(&gdt_p[TSS_DES], (uintptr_t) tss_p); |
| 232 | gdt_tss_setlimit(&gdt_p[TSS_DES], TSS_BASIC_SIZE - 1); |
232 | gdt_tss_setlimit(&gdt_p[TSS_DES], TSS_BASIC_SIZE - 1); |
| 233 | 233 | ||
| 234 | gdtr_load(&gdtr); |
234 | gdtr_load(&gdtr); |
| 235 | idtr_load(&idtr); |
235 | idtr_load(&idtr); |
| 236 | /* |
236 | /* |