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      <para>The majority of the architectures use multi-level page tables,
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      <para>The majority of the architectures use multi-level page tables,
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      which means need to access physical memory several times before getting
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      which means need to access physical memory several times before getting
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      physical address. This fact would make serios performance overhead in
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      physical address. This fact would make serios performance overhead in
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      virtual memory management. To avoid this <link linkend="tlb">Traslation
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      virtual memory management. To avoid this <link linkend="tlb">Traslation
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      Lookaside Buffer (TLB)</link> is used.</para>
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      Lookaside Buffer (TLB)</link> is used.</para>
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      <para>At the moment HelenOS does not support swapping.</para>
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      <para>- pouzivame vypadky stranky k alokaci ramcu on-demand v ramci
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      as_area - na architekturach, ktere to podporuji, podporujeme non-exec
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      stranky</para>
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    </section>
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    </section>
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    <section>
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    <section>
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      <title>Address spaces</title>
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      <title>Address spaces</title>
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      <section>
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      <section>
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        <title>Address spaces and areas</title>
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        <title>Address space areas</title>
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        <para>Each address space consists of mutually disjunctive continuous
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        address space areas. Address space area is precisely defined by its
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        base address and the number of frames is contains.</para>
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        <para>Address space area also has special flags, that define behaviour
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        and permissions on the particular area. <itemizedlist>
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            <listitem>
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              <emphasis>AS_AREA_READ</emphasis>
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               flag indicates reading permission.
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            </listitem>
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            <listitem>
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              <emphasis>AS_AREA_WRITE</emphasis>
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               flag indicates writing permission.
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            </listitem>
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            <listitem>
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              <emphasis>AS_AREA_EXEC</emphasis>
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        <para>- adresovy prostor se sklada z tzv. address space areas
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               flag indicates code execution permission. Some architectures do not support execution persmission restriction. In this case this flag has no effect.
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            </listitem>
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            <listitem>
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        usporadanych v B+stromu; tyto areas popisuji vyuzivane casti
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              <emphasis>AS_AREA_DEVICE</emphasis>
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        adresoveho prostoru patrici do user address space. Kazda cast je dana
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               marks area as mapped to the device memory.
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            </listitem>
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        svoji bazovou adresou, velikosti a flagy (rwx/dd).</para>
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          </itemizedlist></para>
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        <para>- uzivatelske thready maji moznost manipulovat se svym adresovym
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        <para>Kernel provides possibility tasks create/expand/shrink/share its
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        prostorem (vytvaret/resizovat/sdilet) as_areas pomoci syscallu</para>
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        address space via the set of syscalls.</para>
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      </section>
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      </section>
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      <section>
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      <section>
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        <title>Address Space ID (ASID)</title>
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        <title>Address Space ID (ASID)</title>
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        <para>- nektery hardware umoznuje rozlisit ruzne adresove prostory od
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        <para>When switching to the different task, kernel also require to
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        sebe (cilem je maximalizovat vyuziti TLB); dela to tak, ze s kazdou
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        switch mappings to the different address space. In case TLB cannot
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        polozkou TLB/strankovacich tabulek sdruzi identifikator adresoveho
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        distinguish address space mappings, all mappings from the old address
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        prostoru (ASID, RID, ppc32 ???). Tyto id mivaji ruznou sirku: 8-bitu
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        space should be flushed, which can create certain uncessary
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        az 24-bitu (kolik ma ppc32?)</para>
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        overhead.</para>
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        <para>- kernel tomu rozumi a sam pouziva abstrakci ASIDu (na ia64 to
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        <para>To avoid this, some architectures have capability to segregate
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        je napr. cislo odvozene od RIDu, na mips32 to je ASID samotny);
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        different address spaces on HW level introducing the ASID (address
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        space ID). On those architectures each TLB record contains an address
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        existence ASIDu je nutnou podminkou pouziti _global_ page hash table
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        space identifier, that tells to which address space this record is
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        mechanismu.</para>
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        applicable.</para>
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        <para>- na vsech arch. plati, ze asidu je mnohem mene, nez teoreticky
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        <para>HelenOS kernel can take advantage of this hardware supported
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        pocet soucasne bezicich tasku ~ adresovych prostoru, takze je
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        identifier by having an ASID abstraction which is connected to the
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        implementovan mechanismus, ktery umoznuje jednomu adresovemu prostoru
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        corresponding architecture identifier. I.e. on ia64 kernel ASID is
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        built from RID (region identifier) and on the mips32 kernel ASID is
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        ASID odebrat a pridelit ho jinemu</para>
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        actually the hardware identifier.</para>
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        <para>- vztah task ~ adresovy prostor: teoreticky existuje moznost, ze
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        <para>Due to the hardware limitations ASID has limited length from 8
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        bits on ia64 to 24 bits on mips32, which makes it impossible to use as
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        je adresovy prostor sdilen vice tasky, avsak tuto moznost nepouzivame
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        unique address space identifier for all tasks running in the system.
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        a neni ani nijak osetrena. Tim padem plati, ze kazdy task ma vlastni
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        In such situations special ASID stealing algoritm is used, which takes
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        adresovy prostor</para>
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        ASID from inactive task and assigns it to the active task.</para>
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      </section>
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      </section>
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    </section>
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    </section>
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    <section>
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    <section>
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      <title>Virtual address translation</title>
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      <title>Virtual address translation</title>
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        <formalpara>
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        <formalpara>
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          <title>Global hash tables</title>
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          <title>Global hash tables</title>
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          <para>- global page hash table: existuje jen jedna v celem systemu
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          <para>- global page hash table: existuje jen jedna v celem systemu
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          (vyuziva ji ia64), pozn. ia64 ma zatim vypnuty VHPT. Pouziva se
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          (vyuziva ji ia64), pozn. ia64 ma zatim vypnuty VHPT. Pouziva se
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          genericke hash table s oddelenymi collision chains</para>
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          genericke hash table s oddelenymi collision chains. ASID support is
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          required to use global hash tables.</para>
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        </formalpara>
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        </formalpara>
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        <para>Thanks to the abstract paging interface, there is possibility
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        <para>Thanks to the abstract paging interface, there is possibility
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        left have more paging implementations, for example B-Tree page
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        left have more paging implementations, for example B-Tree page
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        tables.</para>
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        tables.</para>
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      </section>
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      </section>
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      <section id="tlb">
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      <section id="tlb">
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        <title>Translation Lookaside buffer</title>
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        <title>Translation Lookaside Buffer</title>
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        <para>- TLB cachuji informace ve strankovacich tabulkach; alternativne
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        <para>- TLB cachuji informace ve strankovacich tabulkach; alternativne
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        se lze na strankovaci tabulky (ci ruzne hw rozsireni [e.g. VHPT, ppc32
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        se lze na strankovaci tabulky (ci ruzne hw rozsireni [e.g. VHPT, ppc32
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        hw hash table]) divat jako na velke TLB</para>
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        hw hash table]) divat jako na velke TLB</para>
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        Black et al., "Translation Lookaside Buffer Consistency: A Software
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        Black et al., "Translation Lookaside Buffer Consistency: A Software
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        Approach," Proc. Third Int'l Conf. Architectural Support for
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        Approach," Proc. Third Int'l Conf. Architectural Support for
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        Programming Languages and Operating Systems, 1989, pp. 113-122.</para>
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        Programming Languages and Operating Systems, 1989, pp. 113-122.</para>
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        <para>- nutno poznamenat, ze existuji odlehcenejsi verze TLB shootdown
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        <para>- nutno poznamenat, ze existuji odlehcenejsi verze TLB shootdown
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        algoritmu</para>
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        algoritm</para>
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      </section>
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      </section>
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    </section>
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    </section>
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    <section>
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      <title>---</title>
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      <para>At the moment HelenOS does not support swapping.</para>
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      <para>- pouzivame vypadky stranky k alokaci ramcu on-demand v ramci
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      as_area - na architekturach, ktere to podporuji, podporujeme non-exec
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      stranky</para>
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    </section>
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  </section>
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  </section>
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  <!-- End of VM -->
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  <!-- End of VM -->
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  <section>
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  <section>
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        power-of-two sized naturally aligned blocks. These blocks are
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        power-of-two sized naturally aligned blocks. These blocks are
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        organized in an array of lists, in which the list with index i
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        organized in an array of lists, in which the list with index i
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        contains all unallocated blocks of size
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        contains all unallocated blocks of size
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        <mathphrase>2<superscript>i</superscript></mathphrase>. The index i is
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        <mathphrase>2<superscript>i</superscript></mathphrase>. The index i is
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        called the order of block. Should there be two adjacent equally sized
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        called the order of block. Should there be two adjacent equally sized
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        blocks in the list i<mathphrase> </mathphrase>(i.e. buddies), the
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        blocks in the list i<mathphrase />(i.e. buddies), the buddy allocator
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        buddy allocator would coalesce them and put the resulting block in
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        would coalesce them and put the resulting block in list <mathphrase>i
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        list <mathphrase>i + 1</mathphrase>, provided that the resulting block
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        + 1</mathphrase>, provided that the resulting block would be naturally
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        would be naturally aligned. Similarily, when the allocator is asked to
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        aligned. Similarily, when the allocator is asked to allocate a block
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        allocate a block of size
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        <mathphrase>2<superscript>i</superscript></mathphrase>, it first tries
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        of size <mathphrase>2<superscript>i</superscript></mathphrase>, it
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        to satisfy the request from the list with index i. If the request
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        first tries to satisfy the request from the list with index i. If the
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        cannot be satisfied (i.e. the list i is empty), the buddy allocator
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        request cannot be satisfied (i.e. the list i is empty), the buddy
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        will try to allocate and split a larger block from the list with index
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        allocator will try to allocate and split a larger block from the list
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        i + 1. Both of these algorithms are recursive. The recursion ends
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        with index i + 1. Both of these algorithms are recursive. The
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        either when there are no blocks to coalesce in the former case or when
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        recursion ends either when there are no blocks to coalesce in the
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        there are no blocks that can be split in the latter case.</para>
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        former case or when there are no blocks that can be split in the
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        latter case.</para>
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        <!--graphic fileref="images/mm1.png" format="EPS" /-->
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        <!--graphic fileref="images/mm1.png" format="EPS" /-->
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        <para>This approach greatly reduces external fragmentation of memory
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        <para>This approach greatly reduces external fragmentation of memory
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        and helps in allocating bigger continuous blocks of memory aligned to
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        and helps in allocating bigger continuous blocks of memory aligned to
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          CPU-bound magazine is actually a pair of magazines to avoid
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          CPU-bound magazine is actually a pair of magazines to avoid
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          thrashing when during allocation/deallocatiion of 1 item at the
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          thrashing when during allocation/deallocatiion of 1 item at the
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          magazine size boundary. LIFO order is enforced, which should avoid
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          magazine size boundary. LIFO order is enforced, which should avoid
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          fragmentation as much as possible.</para>
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          fragmentation as much as possible.</para>
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          <para>Another important entity of magazine layer is a full magazine
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          <para>Another important entity of magazine layer is the common full
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          magazine list (also called a depot), that stores full magazines that
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          depot, that stores full magazines which are used by any of the CPU
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          may be used by any of the CPU magazine caches to reload active CPU
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          magazine caches to reload active CPU magazine. Magazine depot can be
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          magazine. This list of magazines can be pre-filled with full
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          pre-filled with full magazines during initialization, but in current
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          magazines during initialization, but in current implementation it is
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          implementation it is filled during object deallocation, when CPU
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          filled during object deallocation, when CPU magazine becomes
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          magazine becomes full.</para>
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          full.</para>
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          <para>Slab allocator control structures are allocated from special
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          <para>Slab allocator control structures are allocated from special
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          slabs, that are marked by special flag, indicating that it should
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          slabs, that are marked by special flag, indicating that it should
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          not be used for slab magazine layer. This is done to avoid possible
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          not be used for slab magazine layer. This is done to avoid possible
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          infinite recursions and deadlock during conventional slab allocaiton
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          infinite recursions and deadlock during conventional slab allocaiton