Subversion Repositories HelenOS

Rev

Rev 2787 | Go to most recent revision | Show entire file | Ignore whitespace | Details | Blame | Last modification | View Log | RSS feed

Rev 2787 Rev 3424
Line 158... Line 158...
158
 * @param v New value of Primary Context Register.
158
 * @param v New value of Primary Context Register.
159
 */
159
 */
160
static inline void mmu_primary_context_write(uint64_t v)
160
static inline void mmu_primary_context_write(uint64_t v)
161
{
161
{
162
    asi_u64_write(ASI_DMMU, VA_PRIMARY_CONTEXT_REG, v);
162
    asi_u64_write(ASI_DMMU, VA_PRIMARY_CONTEXT_REG, v);
163
    flush();
163
    flush_pipeline();
164
}
164
}
165
 
165
 
166
/** Read MMU Secondary Context Register.
166
/** Read MMU Secondary Context Register.
167
 *
167
 *
168
 * @return Current value of Secondary Context Register.
168
 * @return Current value of Secondary Context Register.
Line 177... Line 177...
177
 * @param v New value of Primary Context Register.
177
 * @param v New value of Primary Context Register.
178
 */
178
 */
179
static inline void mmu_secondary_context_write(uint64_t v)
179
static inline void mmu_secondary_context_write(uint64_t v)
180
{
180
{
181
    asi_u64_write(ASI_DMMU, VA_SECONDARY_CONTEXT_REG, v);
181
    asi_u64_write(ASI_DMMU, VA_SECONDARY_CONTEXT_REG, v);
182
    flush();
182
    flush_pipeline();
183
}
183
}
184
 
184
 
185
/** Read IMMU TLB Data Access Register.
185
/** Read IMMU TLB Data Access Register.
186
 *
186
 *
187
 * @param entry TLB Entry index.
187
 * @param entry TLB Entry index.
Line 207... Line 207...
207
    tlb_data_access_addr_t reg;
207
    tlb_data_access_addr_t reg;
208
   
208
   
209
    reg.value = 0;
209
    reg.value = 0;
210
    reg.tlb_entry = entry;
210
    reg.tlb_entry = entry;
211
    asi_u64_write(ASI_ITLB_DATA_ACCESS_REG, reg.value, value);
211
    asi_u64_write(ASI_ITLB_DATA_ACCESS_REG, reg.value, value);
212
    flush();
212
    flush_pipeline();
213
}
213
}
214
 
214
 
215
/** Read DMMU TLB Data Access Register.
215
/** Read DMMU TLB Data Access Register.
216
 *
216
 *
217
 * @param entry TLB Entry index.
217
 * @param entry TLB Entry index.
Line 277... Line 277...
277
 * @param v Value to be written.
277
 * @param v Value to be written.
278
 */
278
 */
279
static inline void itlb_tag_access_write(uint64_t v)
279
static inline void itlb_tag_access_write(uint64_t v)
280
{
280
{
281
    asi_u64_write(ASI_IMMU, VA_IMMU_TAG_ACCESS, v);
281
    asi_u64_write(ASI_IMMU, VA_IMMU_TAG_ACCESS, v);
282
    flush();
282
    flush_pipeline();
283
}
283
}
284
 
284
 
285
/** Read IMMU TLB Tag Access Register.
285
/** Read IMMU TLB Tag Access Register.
286
 *
286
 *
287
 * @return Current value of IMMU TLB Tag Access Register.
287
 * @return Current value of IMMU TLB Tag Access Register.
Line 316... Line 316...
316
 * @param v Value to be written.
316
 * @param v Value to be written.
317
 */
317
 */
318
static inline void itlb_data_in_write(uint64_t v)
318
static inline void itlb_data_in_write(uint64_t v)
319
{
319
{
320
    asi_u64_write(ASI_ITLB_DATA_IN_REG, 0, v);
320
    asi_u64_write(ASI_ITLB_DATA_IN_REG, 0, v);
321
    flush();
321
    flush_pipeline();
322
}
322
}
323
 
323
 
324
/** Write DMMU TLB Data in Register.
324
/** Write DMMU TLB Data in Register.
325
 *
325
 *
326
 * @param v Value to be written.
326
 * @param v Value to be written.
Line 345... Line 345...
345
 * @param v New value of I-SFSR register.
345
 * @param v New value of I-SFSR register.
346
 */
346
 */
347
static inline void itlb_sfsr_write(uint64_t v)
347
static inline void itlb_sfsr_write(uint64_t v)
348
{
348
{
349
    asi_u64_write(ASI_IMMU, VA_IMMU_SFSR, v);
349
    asi_u64_write(ASI_IMMU, VA_IMMU_SFSR, v);
350
    flush();
350
    flush_pipeline();
351
}
351
}
352
 
352
 
353
/** Read DTLB Synchronous Fault Status Register.
353
/** Read DTLB Synchronous Fault Status Register.
354
 *
354
 *
355
 * @return Current content of D-SFSR register.
355
 * @return Current content of D-SFSR register.
Line 398... Line 398...
398
    da.vpn = pg.vpn;
398
    da.vpn = pg.vpn;
399
   
399
   
400
    asi_u64_write(ASI_IMMU_DEMAP, da.value, 0); /* da.value is the
400
    asi_u64_write(ASI_IMMU_DEMAP, da.value, 0); /* da.value is the
401
                             * address within the
401
                             * address within the
402
                             * ASI */
402
                             * ASI */
403
    flush();
403
    flush_pipeline();
404
}
404
}
405
 
405
 
406
/** Perform DMMU TLB Demap Operation.
406
/** Perform DMMU TLB Demap Operation.
407
 *
407
 *
408
 * @param type Selects between context and page demap.
408
 * @param type Selects between context and page demap.