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Rev 4377 Rev 4692
Line 98... Line 98...
98
{
98
{
99
    tlb_invalidate_all();
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    tlb_invalidate_all();
100
}
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}
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101
 
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102
 
103
void tlb_invalidate_pages(asid_t asid, uintptr_t page, count_t cnt)
103
void tlb_invalidate_pages(asid_t asid, uintptr_t page, size_t cnt)
104
{
104
{
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    region_register rr;
105
    region_register rr;
106
    bool restore_rr = false;
106
    bool restore_rr = false;
107
    int b = 0;
107
    int b = 0;
108
    int c = cnt;
108
    int c = cnt;
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 * @param entry     The rest of TLB entry as required by TLB insertion
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 * @param entry     The rest of TLB entry as required by TLB insertion
266
 *          format.
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 *          format.
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 * @param tr        Translation register.
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 * @param tr        Translation register.
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 */
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 */
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void
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void
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itr_mapping_insert(uintptr_t va, asid_t asid, tlb_entry_t entry, index_t tr)
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itr_mapping_insert(uintptr_t va, asid_t asid, tlb_entry_t entry, size_t tr)
271
{
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{
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    tr_mapping_insert(va, asid, entry, false, tr);
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    tr_mapping_insert(va, asid, entry, false, tr);
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}
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}
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/** Insert data into data translation register.
275
/** Insert data into data translation register.
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 * @param entry     The rest of TLB entry as required by TLB insertion
279
 * @param entry     The rest of TLB entry as required by TLB insertion
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 *          format.
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 *          format.
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 * @param tr        Translation register.
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 * @param tr        Translation register.
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 */
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 */
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void
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void
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dtr_mapping_insert(uintptr_t va, asid_t asid, tlb_entry_t entry, index_t tr)
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dtr_mapping_insert(uintptr_t va, asid_t asid, tlb_entry_t entry, size_t tr)
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{
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{
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    tr_mapping_insert(va, asid, entry, true, tr);
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    tr_mapping_insert(va, asid, entry, true, tr);
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}
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}
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/** Insert data into instruction or data translation register.
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/** Insert data into instruction or data translation register.
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 *          instruction translation register otherwise.
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 *          instruction translation register otherwise.
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 * @param tr        Translation register.
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 * @param tr        Translation register.
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 */
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 */
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void
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void
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tr_mapping_insert(uintptr_t va, asid_t asid, tlb_entry_t entry, bool dtr,
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tr_mapping_insert(uintptr_t va, asid_t asid, tlb_entry_t entry, bool dtr,
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    index_t tr)
301
    size_t tr)
302
{
302
{
303
    region_register rr;
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    region_register rr;
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    bool restore_rr = false;
304
    bool restore_rr = false;
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305
 
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    rr.word = rr_read(VA2VRN(va));
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    rr.word = rr_read(VA2VRN(va));
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 *          translation cache otherwise.
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 *          translation cache otherwise.
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 * @param tr        Translation register if dtr is true, ignored otherwise.
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 * @param tr        Translation register if dtr is true, ignored otherwise.
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 */
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 */
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void
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void
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dtlb_kernel_mapping_insert(uintptr_t page, uintptr_t frame, bool dtr,
355
dtlb_kernel_mapping_insert(uintptr_t page, uintptr_t frame, bool dtr,
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    index_t tr)
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    size_t tr)
357
{
357
{
358
    tlb_entry_t entry;
358
    tlb_entry_t entry;
359
   
359
   
360
    entry.word[0] = 0;
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    entry.word[0] = 0;
361
    entry.word[1] = 0;
361
    entry.word[1] = 0;
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 * Purge DTR entries used by the kernel.
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 * Purge DTR entries used by the kernel.
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 *
381
 *
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 * @param page      Virtual page address including VRN bits.
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 * @param page      Virtual page address including VRN bits.
383
 * @param width     Width of the purge in bits.
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 * @param width     Width of the purge in bits.
384
 */
384
 */
385
void dtr_purge(uintptr_t page, count_t width)
385
void dtr_purge(uintptr_t page, size_t width)
386
{
386
{
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    asm volatile ("ptr.d %0, %1\n" : : "r" (page), "r" (width << 2));
387
    asm volatile ("ptr.d %0, %1\n" : : "r" (page), "r" (width << 2));
388
}
388
}
389
 
389
 
390
 
390
 
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        }
708
        }
709
    }
709
    }
710
    page_table_unlock(AS, true);
710
    page_table_unlock(AS, true);
711
}
711
}
712
 
712
 
-
 
713
/** Data access rights fault handler.
-
 
714
 *
-
 
715
 * @param vector Interruption vector.
-
 
716
 * @param istate Structure with saved interruption state.
-
 
717
 */
-
 
718
void data_access_rights_fault(uint64_t vector, istate_t *istate)
-
 
719
{
-
 
720
    region_register rr;
-
 
721
    rid_t rid;
-
 
722
    uintptr_t va;
-
 
723
    pte_t *t;
-
 
724
 
-
 
725
    va = istate->cr_ifa;    /* faulting address */
-
 
726
    rr.word = rr_read(VA2VRN(va));
-
 
727
    rid = rr.map.rid;
-
 
728
 
-
 
729
    /*
-
 
730
     * Assume a write to a read-only page.
-
 
731
     */
-
 
732
    page_table_lock(AS, true);
-
 
733
    t = page_mapping_find(AS, va);
-
 
734
    ASSERT(t && t->p);
-
 
735
    ASSERT(!t->w);
-
 
736
    if (as_page_fault(va, PF_ACCESS_WRITE, istate) == AS_PF_FAULT) {
-
 
737
        fault_if_from_uspace(istate, "Page fault at %p.", va);
-
 
738
        panic("%s: va=%p, rid=%d, iip=%p.", __func__, va, rid,
-
 
739
            istate->cr_iip);
-
 
740
    }
-
 
741
    page_table_unlock(AS, true);
-
 
742
}
-
 
743
 
713
/** Page not present fault handler.
744
/** Page not present fault handler.
714
 *
745
 *
715
 * @param vector Interruption vector.
746
 * @param vector Interruption vector.
716
 * @param istate Structure with saved interruption state.
747
 * @param istate Structure with saved interruption state.
717
 */
748
 */