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| Rev 1735 | Rev 1780 | ||
|---|---|---|---|
| Line 54... | Line 54... | ||
| 54 | 54 | ||
| 55 | /* |
55 | /* |
| 56 | * Interrupt and exception dispatching. |
56 | * Interrupt and exception dispatching. |
| 57 | */ |
57 | */ |
| 58 | 58 | ||
| 59 | void (* disable_irqs_function)(__u16 irqmask) = NULL; |
59 | void (* disable_irqs_function)(uint16_t irqmask) = NULL; |
| 60 | void (* enable_irqs_function)(__u16 irqmask) = NULL; |
60 | void (* enable_irqs_function)(uint16_t irqmask) = NULL; |
| 61 | void (* eoi_function)(void) = NULL; |
61 | void (* eoi_function)(void) = NULL; |
| 62 | 62 | ||
| 63 | void PRINT_INFO_ERRCODE(istate_t *istate) |
63 | void PRINT_INFO_ERRCODE(istate_t *istate) |
| 64 | { |
64 | { |
| 65 | char *symbol = get_symtab_entry(istate->eip); |
65 | char *symbol = get_symtab_entry(istate->eip); |
| Line 127... | Line 127... | ||
| 127 | panic("stack fault\n"); |
127 | panic("stack fault\n"); |
| 128 | } |
128 | } |
| 129 | 129 | ||
| 130 | void simd_fp_exception(int n, istate_t *istate) |
130 | void simd_fp_exception(int n, istate_t *istate) |
| 131 | { |
131 | { |
| 132 | __u32 mxcsr; |
132 | uint32_t mxcsr; |
| 133 | asm |
133 | asm |
| 134 | ( |
134 | ( |
| 135 | "stmxcsr %0;\n" |
135 | "stmxcsr %0;\n" |
| 136 | :"=m"(mxcsr) |
136 | :"=m"(mxcsr) |
| 137 | ); |
137 | ); |
| 138 | fault_if_from_uspace(istate, "SIMD FP exception(19), MXCSR: %#zx", |
138 | fault_if_from_uspace(istate, "SIMD FP exception(19), MXCSR: %#zx", |
| 139 | (__native)mxcsr); |
139 | (unative_t)mxcsr); |
| 140 | 140 | ||
| 141 | PRINT_INFO_ERRCODE(istate); |
141 | PRINT_INFO_ERRCODE(istate); |
| 142 | printf("MXCSR: %#zx\n",(__native)(mxcsr)); |
142 | printf("MXCSR: %#zx\n",(unative_t)(mxcsr)); |
| 143 | panic("SIMD FP exception(19)\n"); |
143 | panic("SIMD FP exception(19)\n"); |
| 144 | } |
144 | } |
| 145 | 145 | ||
| 146 | void nm_fault(int n, istate_t *istate) |
146 | void nm_fault(int n, istate_t *istate) |
| 147 | { |
147 | { |
| Line 162... | Line 162... | ||
| 162 | { |
162 | { |
| 163 | trap_virtual_eoi(); |
163 | trap_virtual_eoi(); |
| 164 | tlb_shootdown_ipi_recv(); |
164 | tlb_shootdown_ipi_recv(); |
| 165 | } |
165 | } |
| 166 | 166 | ||
| 167 | void trap_virtual_enable_irqs(__u16 irqmask) |
167 | void trap_virtual_enable_irqs(uint16_t irqmask) |
| 168 | { |
168 | { |
| 169 | if (enable_irqs_function) |
169 | if (enable_irqs_function) |
| 170 | enable_irqs_function(irqmask); |
170 | enable_irqs_function(irqmask); |
| 171 | else |
171 | else |
| 172 | panic("no enable_irqs_function\n"); |
172 | panic("no enable_irqs_function\n"); |
| 173 | } |
173 | } |
| 174 | 174 | ||
| 175 | void trap_virtual_disable_irqs(__u16 irqmask) |
175 | void trap_virtual_disable_irqs(uint16_t irqmask) |
| 176 | { |
176 | { |
| 177 | if (disable_irqs_function) |
177 | if (disable_irqs_function) |
| 178 | disable_irqs_function(irqmask); |
178 | disable_irqs_function(irqmask); |
| 179 | else |
179 | else |
| 180 | panic("no disable_irqs_function\n"); |
180 | panic("no disable_irqs_function\n"); |
| Line 195... | Line 195... | ||
| 195 | trap_virtual_eoi(); |
195 | trap_virtual_eoi(); |
| 196 | } |
196 | } |
| 197 | 197 | ||
| 198 | 198 | ||
| 199 | /* Reregister irq to be IPC-ready */ |
199 | /* Reregister irq to be IPC-ready */ |
| 200 | void irq_ipc_bind_arch(__native irq) |
200 | void irq_ipc_bind_arch(unative_t irq) |
| 201 | { |
201 | { |
| 202 | if (irq == IRQ_CLK) |
202 | if (irq == IRQ_CLK) |
| 203 | return; |
203 | return; |
| 204 | exc_register(IVT_IRQBASE+irq, "ipc_int", ipc_int); |
204 | exc_register(IVT_IRQBASE+irq, "ipc_int", ipc_int); |
| 205 | trap_virtual_enable_irqs(1 << irq); |
205 | trap_virtual_enable_irqs(1 << irq); |