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#   else
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#   else
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#       define write_barrier()  asm volatile( "" ::: "memory");
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#       define write_barrier()  asm volatile( "" ::: "memory");
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#   endif
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#   endif
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#endif
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#endif
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/*
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 * On ia32, the hardware takes care about instruction and data cache coherence,
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 * even on SMP systems.  We issue a write barrier to be sure that writes
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 * queueing in the store buffer drain to the memory (even though it would be
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 * sufficient for them to drain to the D-cache).
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 */
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#define smc_coherence(a)        write_barrier()
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#define smc_coherence_block(a, l)   write_barrier()
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#endif
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#endif
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/** @}
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/** @}
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 */
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 */