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Line 447... Line 447...
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/*
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/*
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 * Spills the window at CWP + 2 to the kernel stack. This macro is to be
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 * Spills the window at CWP + 2 to the kernel stack. This macro is to be
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 * used before doing SAVE when the spill trap is undesirable.
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 * used before doing SAVE when the spill trap is undesirable.
-
 
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 * 
-
 
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 * Parameters:
-
 
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 * 	tmpreg1		global register to be used for scratching purposes
-
 
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 * 	tmpreg2		global register to be used for scratching purposes
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 */
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 */
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.macro INLINE_SPILL
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.macro INLINE_SPILL tmpreg1, tmpreg2
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	! CWP := CWP + 2
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	! CWP := CWP + 2
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	rdpr %cwp, %g3
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	rdpr %cwp, \tmpreg2
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	add %g3, 2, %g3
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	add \tmpreg2, 2, \tmpreg1
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	and %g3, NWINDOWS - 1, %g3		! modulo NWINDOWS
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	and \tmpreg1, NWINDOWS - 1, \tmpreg1		! modulo NWINDOWS
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	wrpr %g3, %cwp
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	wrpr \tmpreg1, %cwp
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	! spill to kernel stack
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	! spill to kernel stack
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	stx %l0, [%sp + STACK_BIAS + L0_OFFSET]	
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	stx %l0, [%sp + STACK_BIAS + L0_OFFSET]	
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	stx %l1, [%sp + STACK_BIAS + L1_OFFSET]
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	stx %l1, [%sp + STACK_BIAS + L1_OFFSET]
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	stx %l2, [%sp + STACK_BIAS + L2_OFFSET]
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	stx %l2, [%sp + STACK_BIAS + L2_OFFSET]
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	stx %i5, [%sp + STACK_BIAS + I5_OFFSET]
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	stx %i5, [%sp + STACK_BIAS + I5_OFFSET]
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	stx %i6, [%sp + STACK_BIAS + I6_OFFSET]
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	stx %i6, [%sp + STACK_BIAS + I6_OFFSET]
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	stx %i7, [%sp + STACK_BIAS + I7_OFFSET]
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	stx %i7, [%sp + STACK_BIAS + I7_OFFSET]
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481
 
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	! CWP := CWP - 2
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	! CWP := CWP - 2
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	add %g3, NWINDOWS - 2, %g3
-
 
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	and %g3, NWINDOWS - 1, %g3		! modulo NWINDOWS
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	wrpr %g3, %cwp
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	wrpr \tmpreg2, %cwp
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484
 
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	saved
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	saved
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.endm
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.endm
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487
 
486
/*
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/*
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 * Fill the window at CWP - 1 from the kernel stack. This macro is to be
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 * Fill the window at CWP - 1 from the kernel stack. This macro is to be
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 * used before doing RESTORE when the fill trap is undesirable.
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 * used before doing RESTORE when the fill trap is undesirable.
-
 
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 * 
-
 
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 * Parameters:
-
 
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 * 	tmpreg1		global register to be used for scratching purposes
-
 
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 * 	tmpreg2		global register to be used for scratching purposes
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 */
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 */
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.macro INLINE_FILL
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.macro INLINE_FILL tmpreg1, tmpreg2
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	! CWP := CWP - 1
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	! CWP := CWP - 1
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	rdpr %cwp, %g3
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	rdpr %cwp, \tmpreg2
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	add %g3, NWINDOWS - 1, %g3
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	add \tmpreg2, NWINDOWS - 1, \tmpreg1
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	and %g3, NWINDOWS - 1, %g3
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	and \tmpreg1, NWINDOWS - 1, \tmpreg1
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	wrpr %g3, %cwp
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	wrpr \tmpreg1, %cwp
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	! fill
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	! fill from kernel stack
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	ldx [%sp + STACK_BIAS + L0_OFFSET], %l0
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	ldx [%sp + STACK_BIAS + L0_OFFSET], %l0
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	ldx [%sp + STACK_BIAS + L1_OFFSET], %l1
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	ldx [%sp + STACK_BIAS + L1_OFFSET], %l1
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	ldx [%sp + STACK_BIAS + L2_OFFSET], %l2
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	ldx [%sp + STACK_BIAS + L2_OFFSET], %l2
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	ldx [%sp + STACK_BIAS + L3_OFFSET], %l3
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	ldx [%sp + STACK_BIAS + L3_OFFSET], %l3
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	ldx [%sp + STACK_BIAS + L4_OFFSET], %l4
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	ldx [%sp + STACK_BIAS + L4_OFFSET], %l4
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	ldx [%sp + STACK_BIAS + I5_OFFSET], %i5
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	ldx [%sp + STACK_BIAS + I5_OFFSET], %i5
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	ldx [%sp + STACK_BIAS + I6_OFFSET], %i6
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	ldx [%sp + STACK_BIAS + I6_OFFSET], %i6
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	ldx [%sp + STACK_BIAS + I7_OFFSET], %i7
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	ldx [%sp + STACK_BIAS + I7_OFFSET], %i7
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	! CWP := CWP + 1
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	! CWP := CWP + 1
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	add %g3, 1, %g3
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	and %g3, NWINDOWS - 1, %g3
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	wrpr %g3, %cwp
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	wrpr \tmpreg2, %cwp
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	restored
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	restored
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.endm
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.endm
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/*
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/*
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	/* prevent unnecessary CLEANWIN exceptions */
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	/* prevent unnecessary CLEANWIN exceptions */
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	wrpr %g0, WSTATE_OTHER(0) | WSTATE_NORMAL(0), %wstate
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	wrpr %g0, WSTATE_OTHER(0) | WSTATE_NORMAL(0), %wstate
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1:
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1:
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	/*
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	/*
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	 * Prevent SAVE instruction from causing a spill exception. If the
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	 * Prevent SAVE instruction from causing a spill exception. If the
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	 * CANSAVE register is zero, explicitly spill the current register
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	 * CANSAVE register is zero, explicitly spill register window
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	 * window.
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	 * at CWP + 2.
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	 */
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	 */
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	rdpr %cansave, %g3
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	rdpr %cansave, %g3
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	brnz %g3, 2f
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	brnz %g3, 2f
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	nop
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	nop
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	INLINE_SPILL
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	INLINE_SPILL %g3, %g4
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2:
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2:
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	/* ask for new register window */
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	/* ask for new register window */
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	save %sp, -PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE, %sp
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	save %sp, -PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE, %sp
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	rd %y, %g4
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	rd %y, %g4
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	stx %g4, [%sp + PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE + STACK_BIAS + SAVED_Y]
583
	stx %g4, [%sp + PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE + STACK_BIAS + SAVED_Y]
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	/* switch to TL = 0, explicitly enable FPU */
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	/* switch to TL = 0, explicitly enable FPU */
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	wrpr %g0, 0, %tl
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	wrpr %g0, 0, %tl
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	wrpr %g0, 0, %gl
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	wrpr %g0, PSTATE_PRIV_BIT | PSTATE_PEF_BIT, %pstate
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	wrpr %g0, PSTATE_PRIV_BIT | PSTATE_PEF_BIT, %pstate
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	/* g1 -> l1, ..., g7 -> l7 */
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	/* g1 -> l1, ..., g7 -> l7 */
586
	SAVE_GLOBALS
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	SAVE_GLOBALS
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	ldx [%sp + PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE + STACK_BIAS + SAVED_I6], %i6
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	ldx [%sp + PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE + STACK_BIAS + SAVED_I6], %i6
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	ldx [%sp + PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE + STACK_BIAS + SAVED_I7], %i7
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	ldx [%sp + PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE + STACK_BIAS + SAVED_I7], %i7
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666
 
662
4:
667
4:
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	/*
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	/*
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	 * Prevent RESTORE instruction from causing a spill exception. If the
669
	 * Prevent RESTORE instruction from causing a fill exception. If the
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	 * CANRESTORE register is zero, explicitly spill the current register
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	 * CANRESTORE register is zero, explicitly fill register window
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	 * window.
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	 * at CWP - 1.
667
	 */
672
	 */
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	rdpr %canrestore, %g1
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	rdpr %canrestore, %g1
669
	brnz %g1, 5f
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	brnz %g1, 5f
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	nop
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	nop
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	INLINE_FILL
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	INLINE_FILL %g3, %g4
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677
 
673
5:
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5:
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	restore
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	restore
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	retry
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	retry