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| Rev 1905 | Rev 1906 | ||
|---|---|---|---|
| Line 74... | Line 74... | ||
| 74 | wrpr %g0, PSTATE_PRIV_BIT, %pstate ! Disable interrupts and disable 32-bit address masking. |
74 | wrpr %g0, PSTATE_PRIV_BIT, %pstate ! Disable interrupts and disable 32-bit address masking. |
| 75 | 75 | ||
| 76 | wrpr %g0, 0, %pil ! intialize %pil |
76 | wrpr %g0, 0, %pil ! intialize %pil |
| 77 | 77 | ||
| 78 | /* |
78 | /* |
| 79 | * Copy the bootinfo structure passed from the boot loader |
- | |
| 80 | * to the kernel bootinfo structure. |
- | |
| 81 | */ |
- | |
| 82 | brz %l7, 0f ! skip if you are not the bootstrap CPU |
- | |
| 83 | nop |
- | |
| 84 | - | ||
| 85 | sethi %hi(bootinfo), %o0 |
- | |
| 86 | call memcpy |
- | |
| 87 | or %o0, %lo(bootinfo), %o0 |
- | |
| 88 | 0: |
- | |
| 89 | - | ||
| 90 | /* |
- | |
| 91 | * Switch to kernel trap table. |
79 | * Switch to kernel trap table. |
| 92 | */ |
80 | */ |
| 93 | sethi %hi(trap_table), %g1 |
81 | sethi %hi(trap_table), %g1 |
| 94 | wrpr %g1, %lo(trap_table), %tba |
82 | wrpr %g1, %lo(trap_table), %tba |
| 95 | 83 | ||
| Line 207... | Line 195... | ||
| 207 | ! write ITLB data and install the permanent kernel mapping in context 0 |
195 | ! write ITLB data and install the permanent kernel mapping in context 0 |
| 208 | SET_TLB_DATA(g1, g2, TTE_L) ! use non-global mapping |
196 | SET_TLB_DATA(g1, g2, TTE_L) ! use non-global mapping |
| 209 | stxa %g1, [%g0] ASI_ITLB_DATA_IN_REG |
197 | stxa %g1, [%g0] ASI_ITLB_DATA_IN_REG |
| 210 | flush %g5 |
198 | flush %g5 |
| 211 | 199 | ||
| 212 | ! switch to context 0 |
- | |
| 213 | stxa %g0, [VA_PRIMARY_CONTEXT_REG] %asi ! ASI_DMMU is correct here !!! |
- | |
| 214 | flush %g5 |
- | |
| 215 | - | ||
| 216 | ! ensure nucleus mapping |
200 | ! enter nucleus - using context 0 |
| 217 | wrpr %g0, 1, %tl |
201 | wrpr %g0, 1, %tl |
| 218 | 202 | ||
| 219 | ! set context 1 in the primary context register |
- | |
| 220 | mov MEM_CONTEXT_TEMP, %g1 |
- | |
| 221 | stxa %g1, [VA_PRIMARY_CONTEXT_REG] %asi ! ASI_DMMU is correct here !!! |
- | |
| 222 | flush %g5 |
- | |
| 223 | - | ||
| 224 | ! demap context 1 |
203 | ! demap context 1 |
| 225 | SET_TLB_DEMAP_CMD(g1, TLB_DEMAP_PRIMARY) |
204 | SET_TLB_DEMAP_CMD(g1, TLB_DEMAP_PRIMARY) |
| 226 | stxa %g0, [%g1] ASI_IMMU_DEMAP |
205 | stxa %g0, [%g1] ASI_IMMU_DEMAP |
| 227 | flush %g5 |
206 | flush %g5 |
| 228 | 207 | ||
| 229 | ! set context 0 in the primary context register |
208 | ! set context 0 in the primary context register |
| 230 | stxa %g0, [VA_PRIMARY_CONTEXT_REG] %asi ! ASI_DMMU is correct here !!! |
209 | stxa %g0, [VA_PRIMARY_CONTEXT_REG] %asi ! ASI_DMMU is correct here !!! |
| 231 | flush %g5 |
210 | flush %g5 |
| 232 | 211 | ||
| 233 | ! set TL back to 0 |
212 | ! leave nucleus - using primary context, i.e. context 0 |
| 234 | wrpr %g0, 0, %tl |
213 | wrpr %g0, 0, %tl |
| 235 | 214 | ||
| 236 | brz %l7, 1f ! skip if you are not the bootstrap CPU |
215 | brz %l7, 1f ! skip if you are not the bootstrap CPU |
| 237 | nop |
216 | nop |
| 238 | 217 | ||
| - | 218 | sethi %hi(bootinfo), %o0 |
|
| - | 219 | call memcpy ! copy bootinfo |
|
| - | 220 | or %o0, %lo(bootinfo), %o0 |
|
| - | 221 | ||
| 239 | call arch_pre_main |
222 | call arch_pre_main |
| 240 | nop |
223 | nop |
| 241 | 224 | ||
| 242 | call main_bsp |
225 | call main_bsp |
| 243 | nop |
226 | nop |
| Line 269... | Line 252... | ||
| 269 | ldx [%g2], %g3 |
252 | ldx [%g2], %g3 |
| 270 | cmp %g3, %g1 |
253 | cmp %g3, %g1 |
| 271 | bne 2b |
254 | bne 2b |
| 272 | nop |
255 | nop |
| 273 | 256 | ||
| 274 | - | ||
| 275 | /* |
257 | /* |
| 276 | * Configure stack for the AP. |
258 | * Configure stack for the AP. |
| 277 | * The AP is expected to use the stack saved |
259 | * The AP is expected to use the stack saved |
| 278 | * in the ctx global variable. |
260 | * in the ctx global variable. |
| 279 | */ |
261 | */ |