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Line 39... | Line 39... | ||
39 | #define ITLB_ENTRY_COUNT 64 |
39 | #define ITLB_ENTRY_COUNT 64 |
40 | #define DTLB_ENTRY_COUNT 64 |
40 | #define DTLB_ENTRY_COUNT 64 |
41 | #define DTLB_MAX_LOCKED_ENTRIES DTLB_ENTRY_COUNT |
41 | #define DTLB_MAX_LOCKED_ENTRIES DTLB_ENTRY_COUNT |
42 | #endif |
42 | #endif |
43 | 43 | ||
44 | /** DT16 is the only of the three DMMU caches that can hold locked entries. */ |
44 | /** DT16 is the only of the three DMMUs that can hold locked entries. */ |
45 | #if defined (US3) |
45 | #if defined (US3) |
46 | #define DTLB_MAX_LOCKED_ENTRIES 16 |
46 | #define DTLB_MAX_LOCKED_ENTRIES 16 |
47 | #endif |
47 | #endif |
48 | 48 | ||
49 | #define MEM_CONTEXT_KERNEL 0 |
49 | #define MEM_CONTEXT_KERNEL 0 |
Line 638... | Line 638... | ||
638 | #endif /* !def __ASM__ */ |
638 | #endif /* !def __ASM__ */ |
639 | 639 | ||
640 | #endif |
640 | #endif |
641 | 641 | ||
642 | /** @} |
642 | /** @} |
643 | */ |
- | |
644 | 643 | */ |
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- | 644 |