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33 | */ |
33 | */ |
34 | 34 | ||
35 | #ifndef KERN_sparc64_TLB_H_ |
35 | #ifndef KERN_sparc64_TLB_H_ |
36 | #define KERN_sparc64_TLB_H_ |
36 | #define KERN_sparc64_TLB_H_ |
37 | 37 | ||
- | 38 | #if defined (US) |
|
38 | #define ITLB_ENTRY_COUNT 64 |
39 | #define ITLB_ENTRY_COUNT 64 |
39 | #define DTLB_ENTRY_COUNT 64 |
40 | #define DTLB_ENTRY_COUNT 64 |
- | 41 | #define DTLB_MAX_LOCKED_ENTRIES DTLB_ENTRY_COUNT |
|
- | 42 | #endif |
|
- | 43 | ||
- | 44 | /** DT16 is the only of the three DMMU caches that can hold locked entries. */ |
|
- | 45 | #if defined (US3) |
|
- | 46 | #define DTLB_MAX_LOCKED_ENTRIES 16 |
|
- | 47 | #endif |
|
40 | 48 | ||
41 | #define MEM_CONTEXT_KERNEL 0 |
49 | #define MEM_CONTEXT_KERNEL 0 |
42 | #define MEM_CONTEXT_TEMP 1 |
50 | #define MEM_CONTEXT_TEMP 1 |
43 | 51 | ||
44 | /** Page sizes. */ |
52 | /** Page sizes. */ |
Line 51... | Line 59... | ||
51 | #define KERNEL_PAGE_WIDTH 22 /* 4M */ |
59 | #define KERNEL_PAGE_WIDTH 22 /* 4M */ |
52 | 60 | ||
53 | /* TLB Demap Operation types. */ |
61 | /* TLB Demap Operation types. */ |
54 | #define TLB_DEMAP_PAGE 0 |
62 | #define TLB_DEMAP_PAGE 0 |
55 | #define TLB_DEMAP_CONTEXT 1 |
63 | #define TLB_DEMAP_CONTEXT 1 |
- | 64 | #if defined (US3) |
|
- | 65 | #define TLB_DEMAP_ALL 2 |
|
- | 66 | #endif |
|
56 | 67 | ||
57 | #define TLB_DEMAP_TYPE_SHIFT 6 |
68 | #define TLB_DEMAP_TYPE_SHIFT 6 |
58 | 69 | ||
59 | /* TLB Demap Operation Context register encodings. */ |
70 | /* TLB Demap Operation Context register encodings. */ |
60 | #define TLB_DEMAP_PRIMARY 0 |
71 | #define TLB_DEMAP_PRIMARY 0 |
61 | #define TLB_DEMAP_SECONDARY 1 |
72 | #define TLB_DEMAP_SECONDARY 1 |
62 | #define TLB_DEMAP_NUCLEUS 2 |
73 | #define TLB_DEMAP_NUCLEUS 2 |
63 | 74 | ||
64 | /* there are more TLBs in one MMU in US3, their codes are defined here */ |
75 | /* There are more TLBs in one MMU in US3, their codes are defined here. */ |
65 | #if defined (US3) |
76 | #if defined (US3) |
66 | /* D-MMU: one 16-entry TLB and two 512-entry TLBs */ |
77 | /* D-MMU: one 16-entry TLB and two 512-entry TLBs */ |
67 | #define TLB_DT16 0 |
78 | #define TLB_DT16 0 |
68 | #define TLB_DT512_1 2 |
79 | #define TLB_DT512_0 2 |
69 | #define TLB_DT512_2 3 |
80 | #define TLB_DT512_1 3 |
70 | 81 | ||
71 | /* I-MMU: one 16-entry TLB and one 128-entry TLB */ |
82 | /* I-MMU: one 16-entry TLB and one 128-entry TLB */ |
72 | #define TLB_IT16 0 |
83 | #define TLB_IT16 0 |
73 | #define TLB_IT128 2 |
84 | #define TLB_IT128 2 |
74 | #endif |
85 | #endif |
75 | 86 | ||
76 | #define TLB_DEMAP_CONTEXT_SHIFT 4 |
87 | #define TLB_DEMAP_CONTEXT_SHIFT 4 |
77 | 88 | ||
78 | /* TLB Tag Access shifts */ |
89 | /* TLB Tag Access shifts */ |
Line 161... | Line 172... | ||
161 | 172 | ||
162 | #endif |
173 | #endif |
163 | 174 | ||
164 | /** I-/D-TLB Tag Read Register. */ |
175 | /** I-/D-TLB Tag Read Register. */ |
165 | union tlb_tag_read_reg { |
176 | union tlb_tag_read_reg { |
- | 177 | // TODO have a look at how non-8kB pages will be treated |
|
166 | uint64_t value; |
178 | uint64_t value; |
167 | struct { |
179 | struct { |
168 | uint64_t vpn : 51; /**< Virtual Address bits 63:13. */ |
180 | uint64_t vpn : 51; /**< Virtual Address bits 63:13. */ |
169 | unsigned context : 13; /**< Context identifier. */ |
181 | unsigned context : 13; /**< Context identifier. */ |
170 | } __attribute__ ((packed)); |
182 | } __attribute__ ((packed)); |
Line 176... | Line 188... | ||
176 | /** TLB Demap Operation Address. */ |
188 | /** TLB Demap Operation Address. */ |
177 | union tlb_demap_addr { |
189 | union tlb_demap_addr { |
178 | uint64_t value; |
190 | uint64_t value; |
179 | struct { |
191 | struct { |
180 | uint64_t vpn: 51; /**< Virtual Address bits 63:13. */ |
192 | uint64_t vpn: 51; /**< Virtual Address bits 63:13. */ |
- | 193 | #if defined (US) |
|
181 | unsigned : 6; /**< Ignored. */ |
194 | unsigned : 6; /**< Ignored. */ |
182 | unsigned type : 1; /**< The type of demap operation. */ |
195 | unsigned type : 1; /**< The type of demap operation. */ |
- | 196 | #elif defined (US3) |
|
- | 197 | unsigned : 5; /**< Ignored. */ |
|
- | 198 | unsigned type: 2; /**< The type of demap operation. */ |
|
- | 199 | #endif |
|
183 | unsigned context : 2; /**< Context register selection. */ |
200 | unsigned context : 2; /**< Context register selection. */ |
184 | unsigned : 4; /**< Zero. */ |
201 | unsigned : 4; /**< Zero. */ |
185 | } __attribute__ ((packed)); |
202 | } __attribute__ ((packed)); |
186 | }; |
203 | }; |
187 | typedef union tlb_demap_addr tlb_demap_addr_t; |
204 | typedef union tlb_demap_addr tlb_demap_addr_t; |
188 | 205 | ||
189 | /** TLB Synchronous Fault Status Register. */ |
206 | /** TLB Synchronous Fault Status Register. */ |
190 | union tlb_sfsr_reg { |
207 | union tlb_sfsr_reg { |
191 | uint64_t value; |
208 | uint64_t value; |
192 | struct { |
209 | struct { |
- | 210 | #if defined (US) |
|
193 | unsigned long : 40; /**< Implementation dependent. */ |
211 | unsigned long : 40; /**< Implementation dependent. */ |
194 | unsigned asi : 8; /**< ASI. */ |
212 | unsigned asi : 8; /**< ASI. */ |
195 | unsigned : 2; |
213 | unsigned : 2; |
196 | unsigned ft : 7; /**< Fault type. */ |
214 | unsigned ft : 7; /**< Fault type. */ |
- | 215 | #elif defined (US3) |
|
- | 216 | unsigned long : 39; /**< Implementation dependent. */ |
|
- | 217 | unsigned nf : 1; /**< Non-faulting load. */ |
|
- | 218 | unsigned asi : 8; /**< ASI. */ |
|
- | 219 | unsigned tm : 1; /**< I-TLB miss. */ |
|
- | 220 | unsigned : 3; /**< Reserved. */ |
|
- | 221 | unsigned ft : 5; /**< Fault type. */ |
|
- | 222 | #endif |
|
197 | unsigned e : 1; /**< Side-effect bit. */ |
223 | unsigned e : 1; /**< Side-effect bit. */ |
198 | unsigned ct : 2; /**< Context Register selection. */ |
224 | unsigned ct : 2; /**< Context Register selection. */ |
199 | unsigned pr : 1; /**< Privilege bit. */ |
225 | unsigned pr : 1; /**< Privilege bit. */ |
200 | unsigned w : 1; /**< Write bit. */ |
226 | unsigned w : 1; /**< Write bit. */ |
201 | unsigned ow : 1; /**< Overwrite bit. */ |
227 | unsigned ow : 1; /**< Overwrite bit. */ |
Line 370... | Line 396... | ||
370 | flush_pipeline(); |
396 | flush_pipeline(); |
371 | } |
397 | } |
372 | 398 | ||
373 | /** Read DMMU TLB Data Access Register. |
399 | /** Read DMMU TLB Data Access Register. |
374 | * |
400 | * |
375 | * @param tlb TLB number (one of TLB_DT16, TLB_DT512_1, TLB_DT512_2) |
401 | * @param tlb TLB number (one of TLB_DT16, TLB_DT512_0, TLB_DT512_1) |
376 | * @param entry TLB Entry index. |
402 | * @param entry TLB Entry index. |
377 | * |
403 | * |
378 | * @return Current value of specified DMMU TLB Data Access Register. |
404 | * @return Current value of specified DMMU TLB Data Access Register. |
379 | */ |
405 | */ |
380 | static inline uint64_t dtlb_data_access_read(int tlb, index_t entry) |
406 | static inline uint64_t dtlb_data_access_read(int tlb, index_t entry) |
Line 387... | Line 413... | ||
387 | return asi_u64_read(ASI_DTLB_DATA_ACCESS_REG, reg.value); |
413 | return asi_u64_read(ASI_DTLB_DATA_ACCESS_REG, reg.value); |
388 | } |
414 | } |
389 | 415 | ||
390 | /** Write DMMU TLB Data Access Register. |
416 | /** Write DMMU TLB Data Access Register. |
391 | * |
417 | * |
392 | * @param tlb TLB number (one of TLB_DT16, TLB_DT512_1, TLB_DT512_2) |
418 | * @param tlb TLB number (one of TLB_DT16, TLB_DT512_0, TLB_DT512_1) |
393 | * @param entry TLB Entry index. |
419 | * @param entry TLB Entry index. |
394 | * @param value Value to be written. |
420 | * @param value Value to be written. |
395 | */ |
421 | */ |
396 | static inline void dtlb_data_access_write(int tlb, index_t entry, uint64_t value) |
422 | static inline void dtlb_data_access_write(int tlb, index_t entry, uint64_t value) |
397 | { |
423 | { |
Line 421... | Line 447... | ||
421 | return asi_u64_read(ASI_ITLB_TAG_READ_REG, tag.value); |
447 | return asi_u64_read(ASI_ITLB_TAG_READ_REG, tag.value); |
422 | } |
448 | } |
423 | 449 | ||
424 | /** Read DMMU TLB Tag Read Register. |
450 | /** Read DMMU TLB Tag Read Register. |
425 | * |
451 | * |
426 | * @param tlb TLB number (one of TLB_DT16, TLB_DT512_1, TLB_DT512_2) |
452 | * @param tlb TLB number (one of TLB_DT16, TLB_DT512_0, TLB_DT512_1) |
427 | * @param entry TLB Entry index. |
453 | * @param entry TLB Entry index. |
428 | * |
454 | * |
429 | * @return Current value of specified DMMU TLB Tag Read Register. |
455 | * @return Current value of specified DMMU TLB Tag Read Register. |
430 | */ |
456 | */ |
431 | static inline uint64_t dtlb_tag_read_read(int tlb, index_t entry) |
457 | static inline uint64_t dtlb_tag_read_read(int tlb, index_t entry) |
Line 547... | Line 573... | ||
547 | return asi_u64_read(ASI_DMMU, VA_DMMU_SFAR); |
573 | return asi_u64_read(ASI_DMMU, VA_DMMU_SFAR); |
548 | } |
574 | } |
549 | 575 | ||
550 | /** Perform IMMU TLB Demap Operation. |
576 | /** Perform IMMU TLB Demap Operation. |
551 | * |
577 | * |
- | 578 | * @param type |
|
552 | * @param type Selects between context and page demap. |
579 | * Selects between context and page demap |
- | 580 | * (and entire MMU demap on US-III). |
|
553 | * @param context_encoding Specifies which Context register has Context ID for |
581 | * @param context_encoding Specifies which Context register has Context ID for |
554 | * demap. |
582 | * demap. |
555 | * @param page Address which is on the page to be demapped. |
583 | * @param page Address which is on the page to be demapped. |
556 | */ |
584 | */ |
557 | static inline void itlb_demap(int type, int context_encoding, uintptr_t page) |
585 | static inline void itlb_demap(int type, int context_encoding, uintptr_t page) |
Line 572... | Line 600... | ||
572 | flush_pipeline(); |
600 | flush_pipeline(); |
573 | } |
601 | } |
574 | 602 | ||
575 | /** Perform DMMU TLB Demap Operation. |
603 | /** Perform DMMU TLB Demap Operation. |
576 | * |
604 | * |
- | 605 | * @param type |
|
577 | * @param type Selects between context and page demap. |
606 | * Selects between context and page demap |
- | 607 | * (and entire MMU demap on US-III). |
|
578 | * @param context_encoding Specifies which Context register has Context ID for |
608 | * @param context_encoding Specifies which Context register has Context ID for |
579 | * demap. |
609 | * demap. |
580 | * @param page Address which is on the page to be demapped. |
610 | * @param page Address which is on the page to be demapped. |
581 | */ |
611 | */ |
582 | static inline void dtlb_demap(int type, int context_encoding, uintptr_t page) |
612 | static inline void dtlb_demap(int type, int context_encoding, uintptr_t page) |