WebSVN – HelenOS – Diff – /branches/sparc/kernel/arch/sparc64/include/mm/tlb.h

 /* TLB Demap Operation Context register encodings. */
 #define TLB_DEMAP_PRIMARY   0
 #define TLB_DEMAP_SECONDARY 1
 #define TLB_DEMAP_NUCLEUS   2
+/* there are more TLBs in one MMU in US3, their codes are defined here */
+#if defined (US3)
+    /* D-MMU: one 16-entry TLB and two 512-entry TLBs */
+    #define TLB_DT16    0
+    #define TLB_DT512_1 2
+    #define TLB_DT512_2 3
+    /* I-MMU: one 16-entry TLB and one 128-entry TLB */
+    #define TLB_IT16    0
+    #define TLB_IT128   2
+#endif
 #define TLB_DEMAP_CONTEXT_SHIFT 4
 /* TLB Tag Access shifts */
 #define TLB_TAG_ACCESS_CONTEXT_SHIFT    0
 #define TLB_TAG_ACCESS_CONTEXT_MASK ((1 << 13) - 1)
 /** I-/D-TLB Data In/Access Register type. */
 typedef tte_data_t tlb_data_t;
 /** I-/D-TLB Data Access Address in Alternate Space. */
+#if defined (US)
 union tlb_data_access_addr {
     uint64_t value;
     struct {
         uint64_t : 55;
         unsigned tlb_entry : 6;
         unsigned : 3;
     } __attribute__ ((packed));
 };
-typedef union tlb_data_access_addr tlb_data_access_addr_t;
+typedef union tlb_data_access_addr dtlb_data_access_addr_t;
+typedef union tlb_data_access_addr dtlb_tag_read_addr_t;
+typedef union tlb_data_access_addr itlb_data_access_addr_t;
-typedef union tlb_data_access_addr tlb_tag_read_addr_t;
+typedef union tlb_data_access_addr itlb_tag_read_addr_t;
+#elif defined (US3)
+/*
+ * In US3, I-MMU and D-MMU have different formats of the data
+ * access register virtual address. In the corresponding
+ * structures the member variable for the entry number is
+ * called "local_tlb_entry" - it contrast with the "tlb_entry"
+ * for the US data access register VA structure. The rationale
+ * behind this is to prevent careless mistakes in the code
+ * caused by setting only the entry number and not the TLB
+ * number in the US3 code (when taking the code from US).
+ */
+union dtlb_data_access_addr {
+    uint64_t value;
+    struct {
+        uint64_t : 45;
+        unsigned : 1;
+        unsigned tlb_number : 2;
+        unsigned : 4;
+        unsigned local_tlb_entry : 9;
+        unsigned : 3;
+    } __attribute__ ((packed));
+};
+typedef union dtlb_data_access_addr dtlb_data_access_addr_t;
+typedef union dtlb_data_access_addr dtlb_tag_read_addr_t;
+union itlb_data_access_addr {
+    uint64_t value;
+    struct {
+        uint64_t : 45;
+        unsigned : 1;
+        unsigned tlb_number : 2;
+        unsigned : 6;
+        unsigned local_tlb_entry : 7;
+        unsigned : 3;
+    } __attribute__ ((packed));
+};
+typedef union itlb_data_access_addr itlb_data_access_addr_t;
+typedef union itlb_data_access_addr itlb_tag_read_addr_t;
+#endif
 /** I-/D-TLB Tag Read Register. */
 union tlb_tag_read_reg {
     uint64_t value;
     struct {
+{
     asi_u64_write(ASI_DMMU, VA_SECONDARY_CONTEXT_REG, v);
     flush_pipeline();
+}
+#if defined (US)
 /** Read IMMU TLB Data Access Register.
+ *
  * @param entry TLB Entry index.
+ *
  * @return Current value of specified IMMU TLB Data Access Register.
  */
 static inline uint64_t itlb_data_access_read(index_t entry)
+{
-    tlb_data_access_addr_t reg;
+    itlb_data_access_addr_t reg;
     reg.value = 0;
     reg.tlb_entry = entry;
     return asi_u64_read(ASI_ITLB_DATA_ACCESS_REG, reg.value);
+}
  * @param entry TLB Entry index.
  * @param value Value to be written.
  */
 static inline void itlb_data_access_write(index_t entry, uint64_t value)
+{
-    tlb_data_access_addr_t reg;
+    itlb_data_access_addr_t reg;
     reg.value = 0;
     reg.tlb_entry = entry;
     asi_u64_write(ASI_ITLB_DATA_ACCESS_REG, reg.value, value);
     flush_pipeline();
+ *
  * @return Current value of specified DMMU TLB Data Access Register.
  */
 static inline uint64_t dtlb_data_access_read(index_t entry)
+{
-    tlb_data_access_addr_t reg;
+    dtlb_data_access_addr_t reg;
     reg.value = 0;
     reg.tlb_entry = entry;
     return asi_u64_read(ASI_DTLB_DATA_ACCESS_REG, reg.value);
+}
  * @param entry TLB Entry index.
  * @param value Value to be written.
  */
 static inline void dtlb_data_access_write(index_t entry, uint64_t value)
+{
-    tlb_data_access_addr_t reg;
+    dtlb_data_access_addr_t reg;
     reg.value = 0;
     reg.tlb_entry = entry;
     asi_u64_write(ASI_DTLB_DATA_ACCESS_REG, reg.value, value);
     membar();
+ *
  * @return Current value of specified IMMU TLB Tag Read Register.
  */
 static inline uint64_t itlb_tag_read_read(index_t entry)
+{
-    tlb_tag_read_addr_t tag;
+    itlb_tag_read_addr_t tag;
     tag.value = 0;
     tag.tlb_entry = entry;
     return asi_u64_read(ASI_ITLB_TAG_READ_REG, tag.value);
+}
+ *
  * @return Current value of specified DMMU TLB Tag Read Register.
  */
 static inline uint64_t dtlb_tag_read_read(index_t entry)
+{
-    tlb_tag_read_addr_t tag;
+    dtlb_tag_read_addr_t tag;
     tag.value = 0;
     tag.tlb_entry = entry;
     return asi_u64_read(ASI_DTLB_TAG_READ_REG, tag.value);
+}
+#elif defined (US3)
+/** Read IMMU TLB Data Access Register.
+ *
+ * @param tlb TLB number (one of TLB_IT16 or TLB_IT128)
+ * @param entry TLB Entry index.
+ *
+ * @return Current value of specified IMMU TLB Data Access Register.
+ */
+static inline uint64_t itlb_data_access_read(int tlb, index_t entry)
+{
+    itlb_data_access_addr_t reg;
+    reg.value = 0;
+    reg.tlb_number = tlb;
+    reg.local_tlb_entry = entry;
+    return asi_u64_read(ASI_ITLB_DATA_ACCESS_REG, reg.value);
+}
+/** Write IMMU TLB Data Access Register.
+ * @param tlb TLB number (one of TLB_IT16 or TLB_IT128)
+ * @param entry TLB Entry index.
+ * @param value Value to be written.
+ */
+static inline void itlb_data_access_write(int tlb, index_t entry, uint64_t value)
+{
+    itlb_data_access_addr_t reg;
+    reg.value = 0;
+    reg.tlb_number = tlb;
+    reg.local_tlb_entry = entry;
+    asi_u64_write(ASI_ITLB_DATA_ACCESS_REG, reg.value, value);
+    flush_pipeline();
+}
+/** Read DMMU TLB Data Access Register.
+ *
+ * @param tlb TLB number (one of TLB_DT16, TLB_DT512_1, TLB_DT512_2)
+ * @param entry TLB Entry index.
+ *
+ * @return Current value of specified DMMU TLB Data Access Register.
+ */
+static inline uint64_t dtlb_data_access_read(int tlb, index_t entry)
+{
+    dtlb_data_access_addr_t reg;
+    reg.value = 0;
+    reg.tlb_number = tlb;
+    reg.local_tlb_entry = entry;
+    return asi_u64_read(ASI_DTLB_DATA_ACCESS_REG, reg.value);
+}
+/** Write DMMU TLB Data Access Register.
+ *
+ * @param tlb TLB number (one of TLB_DT16, TLB_DT512_1, TLB_DT512_2)
+ * @param entry TLB Entry index.
+ * @param value Value to be written.
+ */
+static inline void dtlb_data_access_write(int tlb, index_t entry, uint64_t value)
+{
+    dtlb_data_access_addr_t reg;
+    reg.value = 0;
+    reg.tlb_number = tlb;
+    reg.local_tlb_entry = entry;
+    asi_u64_write(ASI_DTLB_DATA_ACCESS_REG, reg.value, value);
+    membar();
+}
+/** Read IMMU TLB Tag Read Register.
+ *
+ * @param tlb TLB number (one of TLB_IT16 or TLB_IT128)
+ * @param entry TLB Entry index.
+ *
+ * @return Current value of specified IMMU TLB Tag Read Register.
+ */
+static inline uint64_t itlb_tag_read_read(int tlb, index_t entry)
+{
+    itlb_tag_read_addr_t tag;
+    tag.value = 0;
+    tag.tlb_number = tlb;
+    tag.local_tlb_entry = entry;
+    return asi_u64_read(ASI_ITLB_TAG_READ_REG, tag.value);
+}
+/** Read DMMU TLB Tag Read Register.
+ *
+ * @param tlb TLB number (one of TLB_DT16, TLB_DT512_1, TLB_DT512_2)
+ * @param entry TLB Entry index.
+ *
+ * @return Current value of specified DMMU TLB Tag Read Register.
+ */
+static inline uint64_t dtlb_tag_read_read(int tlb, index_t entry)
+{
+    dtlb_tag_read_addr_t tag;
+    tag.value = 0;
+    tag.tlb_number = tlb;
+    tag.local_tlb_entry = entry;
+    return asi_u64_read(ASI_DTLB_TAG_READ_REG, tag.value);
+}
+#endif
 /** Write IMMU TLB Tag Access Register.
+ *
  * @param v Value to be written.
  */
 static inline void itlb_tag_access_write(uint64_t v)
 #endif /* !def __ASM__ */
 #endif
 /** @}
  */

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(root)/branches/sparc/kernel/arch/sparc64/include/mm/tlb.h – Rev 3343 → 3440