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52 | /* Virtual Addresses within ASI_IMMU. */ |
52 | /* Virtual Addresses within ASI_IMMU. */ |
53 | #define VA_IMMU_TSB_TAG_TARGET 0x0 /**< IMMU TSB tag target register. */ |
53 | #define VA_IMMU_TSB_TAG_TARGET 0x0 /**< IMMU TSB tag target register. */ |
54 | #define VA_IMMU_SFSR 0x18 /**< IMMU sync fault status register. */ |
54 | #define VA_IMMU_SFSR 0x18 /**< IMMU sync fault status register. */ |
55 | #define VA_IMMU_TSB_BASE 0x28 /**< IMMU TSB base register. */ |
55 | #define VA_IMMU_TSB_BASE 0x28 /**< IMMU TSB base register. */ |
56 | #define VA_IMMU_TAG_ACCESS 0x30 /**< IMMU TLB tag access register. */ |
56 | #define VA_IMMU_TAG_ACCESS 0x30 /**< IMMU TLB tag access register. */ |
- | 57 | #if defined (US3) |
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- | 58 | #define VA_IMMU_PRIMARY_EXTENSION 0x48 /**< IMMU TSB primary extension register */ |
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- | 59 | #define VA_IMMU_NUCLEUS_EXTENSION 0x58 /**< IMMU TSB nucleus extension register */ |
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- | 60 | #endif |
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- | 61 | ||
57 | 62 | ||
58 | /* D-MMU ASIs. */ |
63 | /* D-MMU ASIs. */ |
59 | #define ASI_DMMU 0x58 |
64 | #define ASI_DMMU 0x58 |
60 | #define ASI_DMMU_TSB_8KB_PTR_REG 0x59 |
65 | #define ASI_DMMU_TSB_8KB_PTR_REG 0x59 |
61 | #define ASI_DMMU_TSB_64KB_PTR_REG 0x5a |
66 | #define ASI_DMMU_TSB_64KB_PTR_REG 0x5a |
Line 73... | Line 78... | ||
73 | #define VA_DMMU_SFAR 0x20 /**< DMMU sync fault address register. */ |
78 | #define VA_DMMU_SFAR 0x20 /**< DMMU sync fault address register. */ |
74 | #define VA_DMMU_TSB_BASE 0x28 /**< DMMU TSB base register. */ |
79 | #define VA_DMMU_TSB_BASE 0x28 /**< DMMU TSB base register. */ |
75 | #define VA_DMMU_TAG_ACCESS 0x30 /**< DMMU TLB tag access register. */ |
80 | #define VA_DMMU_TAG_ACCESS 0x30 /**< DMMU TLB tag access register. */ |
76 | #define VA_DMMU_VA_WATCHPOINT_REG 0x38 /**< DMMU VA data watchpoint register. */ |
81 | #define VA_DMMU_VA_WATCHPOINT_REG 0x38 /**< DMMU VA data watchpoint register. */ |
77 | #define VA_DMMU_PA_WATCHPOINT_REG 0x40 /**< DMMU PA data watchpoint register. */ |
82 | #define VA_DMMU_PA_WATCHPOINT_REG 0x40 /**< DMMU PA data watchpoint register. */ |
- | 83 | #if defined (US3) |
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- | 84 | #define VA_DMMU_PRIMARY_EXTENSION 0x48 /**< DMMU TSB primary extension register */ |
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- | 85 | #define VA_DMMU_SECONDARY_EXTENSION 0x50 /**< DMMU TSB secondary extension register */ |
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- | 86 | #define VA_DMMU_NUCLEUS_EXTENSION 0x58 /**< DMMU TSB nucleus extension register */ |
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- | 87 | #endif |
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78 | 88 | ||
79 | #ifndef __ASM__ |
89 | #ifndef __ASM__ |
80 | 90 | ||
81 | #include <arch/asm.h> |
91 | #include <arch/asm.h> |
82 | #include <arch/barrier.h> |
92 | #include <arch/barrier.h> |