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31 | #define PCI_STATUS_66MHZ 0x20 /* Support 66 Mhz PCI 2.1 bus */ |
31 | #define PCI_STATUS_66MHZ 0x20 /* Support 66 Mhz PCI 2.1 bus */ |
32 | #define PCI_STATUS_UDF 0x40 /* Support User Definable Features [obsolete] */ |
32 | #define PCI_STATUS_UDF 0x40 /* Support User Definable Features [obsolete] */ |
33 | #define PCI_STATUS_FAST_BACK 0x80 /* Accept fast-back to back */ |
33 | #define PCI_STATUS_FAST_BACK 0x80 /* Accept fast-back to back */ |
34 | #define PCI_STATUS_PARITY 0x100 /* Detected parity error */ |
34 | #define PCI_STATUS_PARITY 0x100 /* Detected parity error */ |
35 | #define PCI_STATUS_DEVSEL_MASK 0x600 /* DEVSEL timing */ |
35 | #define PCI_STATUS_DEVSEL_MASK 0x600 /* DEVSEL timing */ |
36 | #define PCI_STATUS_DEVSEL_FAST 0x000 |
36 | #define PCI_STATUS_DEVSEL_FAST 0x000 |
37 | #define PCI_STATUS_DEVSEL_MEDIUM 0x200 |
37 | #define PCI_STATUS_DEVSEL_MEDIUM 0x200 |
38 | #define PCI_STATUS_DEVSEL_SLOW 0x400 |
38 | #define PCI_STATUS_DEVSEL_SLOW 0x400 |
39 | #define PCI_STATUS_SIG_TARGET_ABORT 0x800 /* Set on target abort */ |
39 | #define PCI_STATUS_SIG_TARGET_ABORT 0x800 /* Set on target abort */ |
40 | #define PCI_STATUS_REC_TARGET_ABORT 0x1000 /* Master ack of " */ |
40 | #define PCI_STATUS_REC_TARGET_ABORT 0x1000 /* Master ack of " */ |
41 | #define PCI_STATUS_REC_MASTER_ABORT 0x2000 /* Set on master abort */ |
41 | #define PCI_STATUS_REC_MASTER_ABORT 0x2000 /* Set on master abort */ |
42 | #define PCI_STATUS_SIG_SYSTEM_ERROR 0x4000 /* Set when we drive SERR */ |
42 | #define PCI_STATUS_SIG_SYSTEM_ERROR 0x4000 /* Set when we drive SERR */ |
43 | #define PCI_STATUS_DETECTED_PARITY 0x8000 /* Set on parity error */ |
43 | #define PCI_STATUS_DETECTED_PARITY 0x8000 /* Set on parity error */ |
44 | 44 | ||
45 | #define PCI_CLASS_REVISION 0x08 /* High 24 bits are class, low 8 |
45 | #define PCI_CLASS_REVISION 0x08 /* High 24 bits are class, low 8 |
46 | revision */ |
46 | revision */ |
47 | #define PCI_REVISION_ID 0x08 /* Revision ID */ |
47 | #define PCI_REVISION_ID 0x08 /* Revision ID */ |
48 | #define PCI_CLASS_PROG 0x09 /* Reg. Level Programming Interface */ |
48 | #define PCI_CLASS_PROG 0x09 /* Reg. Level Programming Interface */ |
49 | #define PCI_CLASS_DEVICE 0x0a /* Device class */ |
49 | #define PCI_CLASS_DEVICE 0x0a /* Device class */ |
50 | 50 | ||
51 | #define PCI_CACHE_LINE_SIZE 0x0c /* 8 bits */ |
51 | #define PCI_CACHE_LINE_SIZE 0x0c /* 8 bits */ |
52 | #define PCI_LATENCY_TIMER 0x0d /* 8 bits */ |
52 | #define PCI_LATENCY_TIMER 0x0d /* 8 bits */ |
53 | #define PCI_HEADER_TYPE 0x0e /* 8 bits */ |
53 | #define PCI_HEADER_TYPE 0x0e /* 8 bits */ |
54 | #define PCI_HEADER_TYPE_NORMAL 0 |
54 | #define PCI_HEADER_TYPE_NORMAL 0 |
Line 85... | Line 85... | ||
85 | /* bit 1 is reserved if address_space = 1 */ |
85 | /* bit 1 is reserved if address_space = 1 */ |
86 | 86 | ||
87 | /* Header type 0 (normal devices) */ |
87 | /* Header type 0 (normal devices) */ |
88 | #define PCI_CARDBUS_CIS 0x28 |
88 | #define PCI_CARDBUS_CIS 0x28 |
89 | #define PCI_SUBSYSTEM_VENDOR_ID 0x2c |
89 | #define PCI_SUBSYSTEM_VENDOR_ID 0x2c |
90 | #define PCI_SUBSYSTEM_ID 0x2e |
90 | #define PCI_SUBSYSTEM_ID 0x2e |
91 | #define PCI_ROM_ADDRESS 0x30 /* Bits 31..11 are address, 10..1 reserved */ |
91 | #define PCI_ROM_ADDRESS 0x30 /* Bits 31..11 are address, 10..1 reserved */ |
92 | #define PCI_ROM_ADDRESS_ENABLE 0x01 |
92 | #define PCI_ROM_ADDRESS_ENABLE 0x01 |
93 | #define PCI_ROM_ADDRESS_MASK (~(pciaddr_t)0x7ff) |
93 | #define PCI_ROM_ADDRESS_MASK (~(pciaddr_t)0x7ff) |
94 | 94 | ||
95 | #define PCI_CAPABILITY_LIST 0x34 /* Offset of first capability list entry */ |
95 | #define PCI_CAPABILITY_LIST 0x34 /* Offset of first capability list entry */ |
Line 133... | Line 133... | ||
133 | #define PCI_BRIDGE_CONTROL 0x3e |
133 | #define PCI_BRIDGE_CONTROL 0x3e |
134 | #define PCI_BRIDGE_CTL_PARITY 0x01 /* Enable parity detection on secondary interface */ |
134 | #define PCI_BRIDGE_CTL_PARITY 0x01 /* Enable parity detection on secondary interface */ |
135 | #define PCI_BRIDGE_CTL_SERR 0x02 /* The same for SERR forwarding */ |
135 | #define PCI_BRIDGE_CTL_SERR 0x02 /* The same for SERR forwarding */ |
136 | #define PCI_BRIDGE_CTL_NO_ISA 0x04 /* Disable bridging of ISA ports */ |
136 | #define PCI_BRIDGE_CTL_NO_ISA 0x04 /* Disable bridging of ISA ports */ |
137 | #define PCI_BRIDGE_CTL_VGA 0x08 /* Forward VGA addresses */ |
137 | #define PCI_BRIDGE_CTL_VGA 0x08 /* Forward VGA addresses */ |
138 | #define PCI_BRIDGE_CTL_MASTER_ABORT 0x20 /* Report master aborts */ |
138 | #define PCI_BRIDGE_CTL_MASTER_ABORT 0x20 /* Report master aborts */ |
139 | #define PCI_BRIDGE_CTL_BUS_RESET 0x40 /* Secondary bus reset */ |
139 | #define PCI_BRIDGE_CTL_BUS_RESET 0x40 /* Secondary bus reset */ |
140 | #define PCI_BRIDGE_CTL_FAST_BACK 0x80 /* Fast Back2Back enabled on secondary interface */ |
140 | #define PCI_BRIDGE_CTL_FAST_BACK 0x80 /* Fast Back2Back enabled on secondary interface */ |
141 | 141 | ||
142 | /* Header type 2 (CardBus bridges) */ |
142 | /* Header type 2 (CardBus bridges) */ |
143 | /* 0x14-0x15 reserved */ |
143 | /* 0x14-0x15 reserved */ |
Line 183... | Line 183... | ||
183 | #define PCI_CAP_ID_AGP 0x02 /* Accelerated Graphics Port */ |
183 | #define PCI_CAP_ID_AGP 0x02 /* Accelerated Graphics Port */ |
184 | #define PCI_CAP_ID_VPD 0x03 /* Vital Product Data */ |
184 | #define PCI_CAP_ID_VPD 0x03 /* Vital Product Data */ |
185 | #define PCI_CAP_ID_SLOTID 0x04 /* Slot Identification */ |
185 | #define PCI_CAP_ID_SLOTID 0x04 /* Slot Identification */ |
186 | #define PCI_CAP_ID_MSI 0x05 /* Message Signalled Interrupts */ |
186 | #define PCI_CAP_ID_MSI 0x05 /* Message Signalled Interrupts */ |
187 | #define PCI_CAP_ID_CHSWP 0x06 /* CompactPCI HotSwap */ |
187 | #define PCI_CAP_ID_CHSWP 0x06 /* CompactPCI HotSwap */ |
188 | #define PCI_CAP_ID_PCIX 0x07 /* PCI-X */ |
188 | #define PCI_CAP_ID_PCIX 0x07 /* PCI-X */ |
189 | #define PCI_CAP_ID_HT 0x08 /* HyperTransport */ |
189 | #define PCI_CAP_ID_HT 0x08 /* HyperTransport */ |
190 | #define PCI_CAP_ID_VNDR 0x09 /* Vendor specific */ |
190 | #define PCI_CAP_ID_VNDR 0x09 /* Vendor specific */ |
191 | #define PCI_CAP_ID_DBG 0x0A /* Debug port */ |
191 | #define PCI_CAP_ID_DBG 0x0A /* Debug port */ |
192 | #define PCI_CAP_ID_CCRC 0x0B /* CompactPCI Central Resource Control */ |
192 | #define PCI_CAP_ID_CCRC 0x0B /* CompactPCI Central Resource Control */ |
193 | #define PCI_CAP_ID_AGP3 0x0E /* AGP 8x */ |
193 | #define PCI_CAP_ID_AGP3 0x0E /* AGP 8x */ |
194 | #define PCI_CAP_ID_EXP 0x10 /* PCI Express */ |
194 | #define PCI_CAP_ID_EXP 0x10 /* PCI Express */ |
Line 247... | Line 247... | ||
247 | #define PCI_AGP_STATUS_AGP3 0x0008 /* AGP3 mode supported */ |
247 | #define PCI_AGP_STATUS_AGP3 0x0008 /* AGP3 mode supported */ |
248 | #define PCI_AGP_STATUS_RATE4 0x0004 /* 4x transfer rate supported (RFU in AGP3 mode) */ |
248 | #define PCI_AGP_STATUS_RATE4 0x0004 /* 4x transfer rate supported (RFU in AGP3 mode) */ |
249 | #define PCI_AGP_STATUS_RATE2 0x0002 /* 2x transfer rate supported (8x in AGP3 mode) */ |
249 | #define PCI_AGP_STATUS_RATE2 0x0002 /* 2x transfer rate supported (8x in AGP3 mode) */ |
250 | #define PCI_AGP_STATUS_RATE1 0x0001 /* 1x transfer rate supported (4x in AGP3 mode) */ |
250 | #define PCI_AGP_STATUS_RATE1 0x0001 /* 1x transfer rate supported (4x in AGP3 mode) */ |
251 | #define PCI_AGP_COMMAND 8 /* Control register */ |
251 | #define PCI_AGP_COMMAND 8 /* Control register */ |
252 | #define PCI_AGP_COMMAND_RQ_MASK 0xff000000 /* Master: Maximum number of requests */ |
252 | #define PCI_AGP_COMMAND_RQ_MASK 0xff000000 /* Master: Maximum number of requests */ |
253 | #define PCI_AGP_COMMAND_ARQSZ_MASK 0xe000 /* log2(optimum async req size in bytes) - 4 */ |
253 | #define PCI_AGP_COMMAND_ARQSZ_MASK 0xe000 /* log2(optimum async req size in bytes) - 4 */ |
254 | #define PCI_AGP_COMMAND_CAL_MASK 0x1c00 /* Calibration cycle timing */ |
254 | #define PCI_AGP_COMMAND_CAL_MASK 0x1c00 /* Calibration cycle timing */ |
255 | #define PCI_AGP_COMMAND_SBA 0x0200 /* Sideband addressing enabled */ |
255 | #define PCI_AGP_COMMAND_SBA 0x0200 /* Sideband addressing enabled */ |
256 | #define PCI_AGP_COMMAND_AGP 0x0100 /* Allow processing of AGP transactions */ |
256 | #define PCI_AGP_COMMAND_AGP 0x0100 /* Allow processing of AGP transactions */ |
257 | #define PCI_AGP_COMMAND_GART64 0x0080 /* 64-bit GART entries enabled */ |
257 | #define PCI_AGP_COMMAND_GART64 0x0080 /* 64-bit GART entries enabled */ |
258 | #define PCI_AGP_COMMAND_64BIT 0x0020 /* Allow generation of 64-bit addr cycles */ |
258 | #define PCI_AGP_COMMAND_64BIT 0x0020 /* Allow generation of 64-bit addr cycles */ |
259 | #define PCI_AGP_COMMAND_FW 0x0010 /* Enable FW transfers */ |
259 | #define PCI_AGP_COMMAND_FW 0x0010 /* Enable FW transfers */ |
260 | #define PCI_AGP_COMMAND_RATE4 0x0004 /* Use 4x rate (RFU in AGP3 mode) */ |
260 | #define PCI_AGP_COMMAND_RATE4 0x0004 /* Use 4x rate (RFU in AGP3 mode) */ |
261 | #define PCI_AGP_COMMAND_RATE2 0x0002 /* Use 2x rate (8x in AGP3 mode) */ |
261 | #define PCI_AGP_COMMAND_RATE2 0x0002 /* Use 2x rate (8x in AGP3 mode) */ |
262 | #define PCI_AGP_COMMAND_RATE1 0x0001 /* Use 1x rate (4x in AGP3 mode) */ |
262 | #define PCI_AGP_COMMAND_RATE1 0x0001 /* Use 1x rate (4x in AGP3 mode) */ |
263 | #define PCI_AGP_SIZEOF 12 |
263 | #define PCI_AGP_SIZEOF 12 |
264 | 264 | ||
Line 281... | Line 281... | ||
281 | #define PCI_MSI_ADDRESS_HI 8 /* Upper 32 bits (if PCI_MSI_FLAGS_64BIT set) */ |
281 | #define PCI_MSI_ADDRESS_HI 8 /* Upper 32 bits (if PCI_MSI_FLAGS_64BIT set) */ |
282 | #define PCI_MSI_DATA_32 8 /* 16 bits of data for 32-bit devices */ |
282 | #define PCI_MSI_DATA_32 8 /* 16 bits of data for 32-bit devices */ |
283 | #define PCI_MSI_DATA_64 12 /* 16 bits of data for 64-bit devices */ |
283 | #define PCI_MSI_DATA_64 12 /* 16 bits of data for 64-bit devices */ |
284 | 284 | ||
285 | /* PCI-X */ |
285 | /* PCI-X */ |
286 | #define PCI_PCIX_COMMAND 2 /* Command register offset */ |
286 | #define PCI_PCIX_COMMAND 2 /* Command register offset */ |
287 | #define PCI_PCIX_COMMAND_DPERE 0x0001 /* Data Parity Error Recover Enable */ |
287 | #define PCI_PCIX_COMMAND_DPERE 0x0001 /* Data Parity Error Recover Enable */ |
288 | #define PCI_PCIX_COMMAND_ERO 0x0002 /* Enable Relaxed Ordering */ |
288 | #define PCI_PCIX_COMMAND_ERO 0x0002 /* Enable Relaxed Ordering */ |
289 | #define PCI_PCIX_COMMAND_MAX_MEM_READ_BYTE_COUNT 0x000c /* Maximum Memory Read Byte Count */ |
289 | #define PCI_PCIX_COMMAND_MAX_MEM_READ_BYTE_COUNT 0x000c /* Maximum Memory Read Byte Count */ |
290 | #define PCI_PCIX_COMMAND_MAX_OUTSTANDING_SPLIT_TRANS 0x0070 |
290 | #define PCI_PCIX_COMMAND_MAX_OUTSTANDING_SPLIT_TRANS 0x0070 |
291 | #define PCI_PCIX_COMMAND_RESERVED 0xf80 |
291 | #define PCI_PCIX_COMMAND_RESERVED 0xf80 |
292 | #define PCI_PCIX_STATUS 4 /* Status register offset */ |
292 | #define PCI_PCIX_STATUS 4 /* Status register offset */ |
293 | #define PCI_PCIX_STATUS_FUNCTION 0x00000007 |
293 | #define PCI_PCIX_STATUS_FUNCTION 0x00000007 |
294 | #define PCI_PCIX_STATUS_DEVICE 0x000000f8 |
294 | #define PCI_PCIX_STATUS_DEVICE 0x000000f8 |
295 | #define PCI_PCIX_STATUS_BUS 0x0000ff00 |
295 | #define PCI_PCIX_STATUS_BUS 0x0000ff00 |
296 | #define PCI_PCIX_STATUS_64BIT 0x00010000 |
296 | #define PCI_PCIX_STATUS_64BIT 0x00010000 |
297 | #define PCI_PCIX_STATUS_133MHZ 0x00020000 |
297 | #define PCI_PCIX_STATUS_133MHZ 0x00020000 |
298 | #define PCI_PCIX_STATUS_SC_DISCARDED 0x00040000 /* Split Completion Discarded */ |
298 | #define PCI_PCIX_STATUS_SC_DISCARDED 0x00040000 /* Split Completion Discarded */ |
299 | #define PCI_PCIX_STATUS_UNEXPECTED_SC 0x00080000 /* Unexpected Split Completion */ |
299 | #define PCI_PCIX_STATUS_UNEXPECTED_SC 0x00080000 /* Unexpected Split Completion */ |
300 | #define PCI_PCIX_STATUS_DEVICE_COMPLEXITY 0x00100000 /* 0 = simple device, 1 = bridge device */ |
300 | #define PCI_PCIX_STATUS_DEVICE_COMPLEXITY 0x00100000 /* 0 = simple device, 1 = bridge device */ |
301 | #define PCI_PCIX_STATUS_DESIGNED_MAX_MEM_READ_BYTE_COUNT 0x00600000 /* 0 = 512 bytes, 1 = 1024, 2 = 2048, 3 = 4096 */ |
301 | #define PCI_PCIX_STATUS_DESIGNED_MAX_MEM_READ_BYTE_COUNT 0x00600000 /* 0 = 512 bytes, 1 = 1024, 2 = 2048, 3 = 4096 */ |
302 | #define PCI_PCIX_STATUS_DESIGNED_MAX_OUTSTANDING_SPLIT_TRANS 0x03800000 |
302 | #define PCI_PCIX_STATUS_DESIGNED_MAX_OUTSTANDING_SPLIT_TRANS 0x03800000 |
303 | #define PCI_PCIX_STATUS_DESIGNED_MAX_CUMULATIVE_READ_SIZE 0x1c000000 |
303 | #define PCI_PCIX_STATUS_DESIGNED_MAX_CUMULATIVE_READ_SIZE 0x1c000000 |
304 | #define PCI_PCIX_STATUS_RCVD_SC_ERR_MESS 0x20000000 /* Received Split Completion Error Message */ |
304 | #define PCI_PCIX_STATUS_RCVD_SC_ERR_MESS 0x20000000 /* Received Split Completion Error Message */ |
305 | #define PCI_PCIX_STATUS_266MHZ 0x40000000 /* 266 MHz capable */ |
305 | #define PCI_PCIX_STATUS_266MHZ 0x40000000 /* 266 MHz capable */ |
306 | #define PCI_PCIX_STATUS_533MHZ 0x80000000 /* 533 MHz capable */ |
306 | #define PCI_PCIX_STATUS_533MHZ 0x80000000 /* 533 MHz capable */ |
307 | #define PCI_PCIX_SIZEOF 4 |
307 | #define PCI_PCIX_SIZEOF 4 |
308 | 308 | ||
309 | /* PCI-X Bridges */ |
309 | /* PCI-X Bridges */ |
310 | #define PCI_PCIX_BRIDGE_SEC_STATUS 2 /* Secondary bus status register offset */ |
310 | #define PCI_PCIX_BRIDGE_SEC_STATUS 2 /* Secondary bus status register offset */ |
311 | #define PCI_PCIX_BRIDGE_SEC_STATUS_64BIT 0x0001 |
311 | #define PCI_PCIX_BRIDGE_SEC_STATUS_64BIT 0x0001 |
312 | #define PCI_PCIX_BRIDGE_SEC_STATUS_133MHZ 0x0002 |
312 | #define PCI_PCIX_BRIDGE_SEC_STATUS_133MHZ 0x0002 |
313 | #define PCI_PCIX_BRIDGE_SEC_STATUS_SC_DISCARDED 0x0004 /* Split Completion Discarded on secondary bus */ |
313 | #define PCI_PCIX_BRIDGE_SEC_STATUS_SC_DISCARDED 0x0004 /* Split Completion Discarded on secondary bus */ |
314 | #define PCI_PCIX_BRIDGE_SEC_STATUS_UNEXPECTED_SC 0x0008 /* Unexpected Split Completion on secondary bus */ |
314 | #define PCI_PCIX_BRIDGE_SEC_STATUS_UNEXPECTED_SC 0x0008 /* Unexpected Split Completion on secondary bus */ |
315 | #define PCI_PCIX_BRIDGE_SEC_STATUS_SC_OVERRUN 0x0010 /* Split Completion Overrun on secondary bus */ |
315 | #define PCI_PCIX_BRIDGE_SEC_STATUS_SC_OVERRUN 0x0010 /* Split Completion Overrun on secondary bus */ |
316 | #define PCI_PCIX_BRIDGE_SEC_STATUS_SPLIT_REQUEST_DELAYED 0x0020 |
316 | #define PCI_PCIX_BRIDGE_SEC_STATUS_SPLIT_REQUEST_DELAYED 0x0020 |
317 | #define PCI_PCIX_BRIDGE_SEC_STATUS_CLOCK_FREQ 0x01c0 |
317 | #define PCI_PCIX_BRIDGE_SEC_STATUS_CLOCK_FREQ 0x01c0 |
318 | #define PCI_PCIX_BRIDGE_SEC_STATUS_RESERVED 0xfe00 |
318 | #define PCI_PCIX_BRIDGE_SEC_STATUS_RESERVED 0xfe00 |
319 | #define PCI_PCIX_BRIDGE_STATUS 4 /* Primary bus status register offset */ |
319 | #define PCI_PCIX_BRIDGE_STATUS 4 /* Primary bus status register offset */ |
320 | #define PCI_PCIX_BRIDGE_STATUS_FUNCTION 0x00000007 |
320 | #define PCI_PCIX_BRIDGE_STATUS_FUNCTION 0x00000007 |
321 | #define PCI_PCIX_BRIDGE_STATUS_DEVICE 0x000000f8 |
321 | #define PCI_PCIX_BRIDGE_STATUS_DEVICE 0x000000f8 |
322 | #define PCI_PCIX_BRIDGE_STATUS_BUS 0x0000ff00 |
322 | #define PCI_PCIX_BRIDGE_STATUS_BUS 0x0000ff00 |
323 | #define PCI_PCIX_BRIDGE_STATUS_64BIT 0x00010000 |
323 | #define PCI_PCIX_BRIDGE_STATUS_64BIT 0x00010000 |
324 | #define PCI_PCIX_BRIDGE_STATUS_133MHZ 0x00020000 |
324 | #define PCI_PCIX_BRIDGE_STATUS_133MHZ 0x00020000 |
325 | #define PCI_PCIX_BRIDGE_STATUS_SC_DISCARDED 0x00040000 /* Split Completion Discarded */ |
325 | #define PCI_PCIX_BRIDGE_STATUS_SC_DISCARDED 0x00040000 /* Split Completion Discarded */ |
326 | #define PCI_PCIX_BRIDGE_STATUS_UNEXPECTED_SC 0x00080000 /* Unexpected Split Completion */ |
326 | #define PCI_PCIX_BRIDGE_STATUS_UNEXPECTED_SC 0x00080000 /* Unexpected Split Completion */ |
327 | #define PCI_PCIX_BRIDGE_STATUS_SC_OVERRUN 0x00100000 /* Split Completion Overrun */ |
327 | #define PCI_PCIX_BRIDGE_STATUS_SC_OVERRUN 0x00100000 /* Split Completion Overrun */ |
328 | #define PCI_PCIX_BRIDGE_STATUS_SPLIT_REQUEST_DELAYED 0x00200000 |
328 | #define PCI_PCIX_BRIDGE_STATUS_SPLIT_REQUEST_DELAYED 0x00200000 |
329 | #define PCI_PCIX_BRIDGE_STATUS_RESERVED 0xffc00000 |
329 | #define PCI_PCIX_BRIDGE_STATUS_RESERVED 0xffc00000 |
330 | #define PCI_PCIX_BRIDGE_UPSTREAM_SPLIT_TRANS_CTRL 8 /* Upstream Split Transaction Register offset */ |
330 | #define PCI_PCIX_BRIDGE_UPSTREAM_SPLIT_TRANS_CTRL 8 /* Upstream Split Transaction Register offset */ |
331 | #define PCI_PCIX_BRIDGE_DOWNSTREAM_SPLIT_TRANS_CTRL 12 /* Downstream Split Transaction Register offset */ |
331 | #define PCI_PCIX_BRIDGE_DOWNSTREAM_SPLIT_TRANS_CTRL 12 /* Downstream Split Transaction Register offset */ |
332 | #define PCI_PCIX_BRIDGE_STR_CAPACITY 0x0000ffff |
332 | #define PCI_PCIX_BRIDGE_STR_CAPACITY 0x0000ffff |
333 | #define PCI_PCIX_BRIDGE_STR_COMMITMENT_LIMIT 0xffff0000 |
333 | #define PCI_PCIX_BRIDGE_STR_COMMITMENT_LIMIT 0xffff0000 |
334 | #define PCI_PCIX_BRIDGE_SIZEOF 12 |
334 | #define PCI_PCIX_BRIDGE_SIZEOF 12 |
335 | 335 | ||
336 | /* HyperTransport (as of spec rev. 2.00) */ |
336 | /* HyperTransport (as of spec rev. 2.00) */ |
Line 499... | Line 499... | ||
499 | #define PCI_HT_SW_CMD_VIBFL 0x0100 /* VIB Flood */ |
499 | #define PCI_HT_SW_CMD_VIBFL 0x0100 /* VIB Flood */ |
500 | #define PCI_HT_SW_CMD_VIBFT 0x0200 /* VIB Fatal */ |
500 | #define PCI_HT_SW_CMD_VIBFT 0x0200 /* VIB Fatal */ |
501 | #define PCI_HT_SW_CMD_VIBNFT 0x0400 /* VIB Nonfatal */ |
501 | #define PCI_HT_SW_CMD_VIBNFT 0x0400 /* VIB Nonfatal */ |
502 | #define PCI_HT_SW_PMASK 4 /* Partition Mask Register */ |
502 | #define PCI_HT_SW_PMASK 4 /* Partition Mask Register */ |
503 | #define PCI_HT_SW_SWINF 8 /* Switch Info Register */ |
503 | #define PCI_HT_SW_SWINF 8 /* Switch Info Register */ |
504 | #define PCI_HT_SW_SWINF_DP 0x0000001f /* Default Port */ |
504 | #define PCI_HT_SW_SWINF_DP 0x0000001f /* Default Port */ |
505 | #define PCI_HT_SW_SWINF_EN 0x00000020 /* Enable Decode */ |
505 | #define PCI_HT_SW_SWINF_EN 0x00000020 /* Enable Decode */ |
506 | #define PCI_HT_SW_SWINF_CR 0x00000040 /* Cold Reset */ |
506 | #define PCI_HT_SW_SWINF_CR 0x00000040 /* Cold Reset */ |
507 | #define PCI_HT_SW_SWINF_PCIDX 0x00000f00 /* Performance Counter Index */ |
507 | #define PCI_HT_SW_SWINF_PCIDX 0x00000f00 /* Performance Counter Index */ |
508 | #define PCI_HT_SW_SWINF_BLRIDX 0x0003f000 /* Base/Limit Range Index */ |
508 | #define PCI_HT_SW_SWINF_BLRIDX 0x0003f000 /* Base/Limit Range Index */ |
509 | #define PCI_HT_SW_SWINF_SBIDX 0x00002000 /* Secondary Base Range Index */ |
509 | #define PCI_HT_SW_SWINF_SBIDX 0x00002000 /* Secondary Base Range Index */ |
510 | #define PCI_HT_SW_SWINF_HP 0x00040000 /* Hot Plug */ |
510 | #define PCI_HT_SW_SWINF_HP 0x00040000 /* Hot Plug */ |
511 | #define PCI_HT_SW_SWINF_HIDE 0x00080000 /* Hide Port */ |
511 | #define PCI_HT_SW_SWINF_HIDE 0x00080000 /* Hide Port */ |
512 | #define PCI_HT_SW_PCD 12 /* Performance Counter Data Register */ |
512 | #define PCI_HT_SW_PCD 12 /* Performance Counter Data Register */ |
513 | #define PCI_HT_SW_BLRD 16 /* Base/Limit Range Data Register */ |
513 | #define PCI_HT_SW_BLRD 16 /* Base/Limit Range Data Register */ |
514 | #define PCI_HT_SW_SBD 20 /* Secondary Base Data Register */ |
514 | #define PCI_HT_SW_SBD 20 /* Secondary Base Data Register */ |
515 | #define PCI_HT_SW_SIZEOF 24 |
515 | #define PCI_HT_SW_SIZEOF 24 |
516 | 516 | ||
Line 543... | Line 543... | ||
543 | #define PCI_HT_IDC_DATA 4 /* Data Register */ |
543 | #define PCI_HT_IDC_DATA 4 /* Data Register */ |
544 | #define PCI_HT_IDC_SIZEOF 8 |
544 | #define PCI_HT_IDC_SIZEOF 8 |
545 | 545 | ||
546 | /* Register indices */ |
546 | /* Register indices */ |
547 | #define PCI_HT_IDC_IDX_LINT 0x01 /* Last Interrupt Register */ |
547 | #define PCI_HT_IDC_IDX_LINT 0x01 /* Last Interrupt Register */ |
548 | #define PCI_HT_IDC_LINT 0x00ff0000 /* Last interrupt definition */ |
548 | #define PCI_HT_IDC_LINT 0x00ff0000 /* Last interrupt definition */ |
549 | #define PCI_HT_IDC_IDX_IDR 0x10 /* Interrupt Definition Registers */ |
549 | #define PCI_HT_IDC_IDX_IDR 0x10 /* Interrupt Definition Registers */ |
550 | /* Low part (at index) */ |
550 | /* Low part (at index) */ |
551 | #define PCI_HT_IDC_IDR_MASK 0x10000001 /* Mask */ |
551 | #define PCI_HT_IDC_IDR_MASK 0x10000001 /* Mask */ |
552 | #define PCI_HT_IDC_IDR_POL 0x10000002 /* Polarity */ |
552 | #define PCI_HT_IDC_IDR_POL 0x10000002 /* Polarity */ |
553 | #define PCI_HT_IDC_IDR_II_2 0x1000001c /* IntrInfo[4:2]: Message Type */ |
553 | #define PCI_HT_IDC_IDR_II_2 0x1000001c /* IntrInfo[4:2]: Message Type */ |
554 | #define PCI_HT_IDC_IDR_II_5 0x10000020 /* IntrInfo[5]: Request EOI */ |
554 | #define PCI_HT_IDC_IDR_II_5 0x10000020 /* IntrInfo[5]: Request EOI */ |
555 | #define PCI_HT_IDC_IDR_II_6 0x00ffffc0 /* IntrInfo[23:6] */ |
555 | #define PCI_HT_IDC_IDR_II_6 0x00ffffc0 /* IntrInfo[23:6] */ |
556 | #define PCI_HT_IDC_IDR_II_24 0xff000000 /* IntrInfo[31:24] */ |
556 | #define PCI_HT_IDC_IDR_II_24 0xff000000 /* IntrInfo[31:24] */ |
557 | /* High part (at index + 1) */ |
557 | /* High part (at index + 1) */ |
558 | #define PCI_HT_IDC_IDR_II_32 0x00ffffff /* IntrInfo[55:32] */ |
558 | #define PCI_HT_IDC_IDR_II_32 0x00ffffff /* IntrInfo[55:32] */ |
559 | #define PCI_HT_IDC_IDR_PASSPW 0x40000000 /* PassPW setting for messages */ |
559 | #define PCI_HT_IDC_IDR_PASSPW 0x40000000 /* PassPW setting for messages */ |
560 | #define PCI_HT_IDC_IDR_WEOI 0x80000000 /* Waiting for EOI */ |
560 | #define PCI_HT_IDC_IDR_WEOI 0x80000000 /* Waiting for EOI */ |
561 | 561 | ||
562 | /* HyperTransport: Revision ID */ |
562 | /* HyperTransport: Revision ID */ |
563 | #define PCI_HT_RID_RID 2 /* Revision Register */ |
563 | #define PCI_HT_RID_RID 2 /* Revision Register */ |
564 | #define PCI_HT_RID_SIZEOF 4 |
564 | #define PCI_HT_RID_SIZEOF 4 |
565 | 565 | ||
Line 568... | Line 568... | ||
568 | #define PCI_HT_UIDC_CE 8 /* Clumping Enable Register */ |
568 | #define PCI_HT_UIDC_CE 8 /* Clumping Enable Register */ |
569 | #define PCI_HT_UIDC_SIZEOF 12 |
569 | #define PCI_HT_UIDC_SIZEOF 12 |
570 | 570 | ||
571 | /* HyperTransport: Extended Configuration Space Access */ |
571 | /* HyperTransport: Extended Configuration Space Access */ |
572 | #define PCI_HT_ECSA_ADDR 4 /* Configuration Address Register */ |
572 | #define PCI_HT_ECSA_ADDR 4 /* Configuration Address Register */ |
573 | #define PCI_HT_ECSA_ADDR_REG 0x00000ffc /* Register */ |
573 | #define PCI_HT_ECSA_ADDR_REG 0x00000ffc /* Register */ |
574 | #define PCI_HT_ECSA_ADDR_FUN 0x00007000 /* Function */ |
574 | #define PCI_HT_ECSA_ADDR_FUN 0x00007000 /* Function */ |
575 | #define PCI_HT_ECSA_ADDR_DEV 0x000f1000 /* Device */ |
575 | #define PCI_HT_ECSA_ADDR_DEV 0x000f1000 /* Device */ |
576 | #define PCI_HT_ECSA_ADDR_BUS 0x0ff00000 /* Bus Number */ |
576 | #define PCI_HT_ECSA_ADDR_BUS 0x0ff00000 /* Bus Number */ |
577 | #define PCI_HT_ECSA_ADDR_TYPE 0x10000000 /* Access Type */ |
577 | #define PCI_HT_ECSA_ADDR_TYPE 0x10000000 /* Access Type */ |
578 | #define PCI_HT_ECSA_DATA 8 /* Configuration Data Register */ |
578 | #define PCI_HT_ECSA_DATA 8 /* Configuration Data Register */ |
579 | #define PCI_HT_ECSA_SIZEOF 12 |
579 | #define PCI_HT_ECSA_SIZEOF 12 |
580 | 580 | ||
581 | /* HyperTransport: Address Mapping */ |
581 | /* HyperTransport: Address Mapping */ |
582 | #define PCI_HT_AM_CMD 2 /* Command Register */ |
582 | #define PCI_HT_AM_CMD 2 /* Command Register */ |
Line 592... | Line 592... | ||
592 | #define PCI_HT_AM_SBW_CTR_ISOC 0x4 /* Isochronous */ |
592 | #define PCI_HT_AM_SBW_CTR_ISOC 0x4 /* Isochronous */ |
593 | #define PCI_HT_AM_SBW_CTR_EN 0x8 /* Enable */ |
593 | #define PCI_HT_AM_SBW_CTR_EN 0x8 /* Enable */ |
594 | 594 | ||
595 | /* HyperTransport: 40-bit Address Mapping */ |
595 | /* HyperTransport: 40-bit Address Mapping */ |
596 | #define PCI_HT_AM40_SBNPW 4 /* Secondary Bus Non-Prefetchable Window Register */ |
596 | #define PCI_HT_AM40_SBNPW 4 /* Secondary Bus Non-Prefetchable Window Register */ |
597 | #define PCI_HT_AM40_SBW_BASE 0x000fffff /* Window Base */ |
597 | #define PCI_HT_AM40_SBW_BASE 0x000fffff /* Window Base */ |
598 | #define PCI_HT_AM40_SBW_CTR 0xf0000000 /* Window Control */ |
598 | #define PCI_HT_AM40_SBW_CTR 0xf0000000 /* Window Control */ |
599 | #define PCI_HT_AM40_SBPW 8 /* Secondary Bus Prefetchable Window Register */ |
599 | #define PCI_HT_AM40_SBPW 8 /* Secondary Bus Prefetchable Window Register */ |
600 | #define PCI_HT_AM40_DMA_PBASE0 12 /* DMA Window Primary Base 0 Register */ |
600 | #define PCI_HT_AM40_DMA_PBASE0 12 /* DMA Window Primary Base 0 Register */ |
601 | #define PCI_HT_AM40_DMA_CTR0 15 /* DMA Window Control 0 Register */ |
601 | #define PCI_HT_AM40_DMA_CTR0 15 /* DMA Window Control 0 Register */ |
602 | #define PCI_HT_AM40_DMA_CTR_CTR 0xf0 /* Window Control */ |
602 | #define PCI_HT_AM40_DMA_CTR_CTR 0xf0 /* Window Control */ |
603 | #define PCI_HT_AM40_DMA_SLIM0 16 /* DMA Window Secondary Limit 0 Register */ |
603 | #define PCI_HT_AM40_DMA_SLIM0 16 /* DMA Window Secondary Limit 0 Register */ |
Line 610... | Line 610... | ||
610 | #define PCI_HT_AM64_DATA_HI 12 /* Data Upper Register */ |
610 | #define PCI_HT_AM64_DATA_HI 12 /* Data Upper Register */ |
611 | #define PCI_HT_AM64_SIZEOF 16 |
611 | #define PCI_HT_AM64_SIZEOF 16 |
612 | 612 | ||
613 | /* Register indices */ |
613 | /* Register indices */ |
614 | #define PCI_HT_AM64_IDX_SBNPW 0x00 /* Secondary Bus Non-Prefetchable Window Register */ |
614 | #define PCI_HT_AM64_IDX_SBNPW 0x00 /* Secondary Bus Non-Prefetchable Window Register */ |
615 | #define PCI_HT_AM64_W_BASE_LO 0xfff00000 /* Window Base Lower */ |
615 | #define PCI_HT_AM64_W_BASE_LO 0xfff00000 /* Window Base Lower */ |
616 | #define PCI_HT_AM64_W_CTR 0x0000000f /* Window Control */ |
616 | #define PCI_HT_AM64_W_CTR 0x0000000f /* Window Control */ |
617 | #define PCI_HT_AM64_IDX_SBPW 0x01 /* Secondary Bus Prefetchable Window Register */ |
617 | #define PCI_HT_AM64_IDX_SBPW 0x01 /* Secondary Bus Prefetchable Window Register */ |
618 | #define PCI_HT_AM64_IDX_PBNPW 0x02 /* Primary Bus Non-Prefetchable Window Register */ |
618 | #define PCI_HT_AM64_IDX_PBNPW 0x02 /* Primary Bus Non-Prefetchable Window Register */ |
619 | #define PCI_HT_AM64_IDX_DMAPB0 0x04 /* DMA Window Primary Base 0 Register */ |
619 | #define PCI_HT_AM64_IDX_DMAPB0 0x04 /* DMA Window Primary Base 0 Register */ |
620 | #define PCI_HT_AM64_IDX_DMASB0 0x05 /* DMA Window Secondary Base 0 Register */ |
620 | #define PCI_HT_AM64_IDX_DMASB0 0x05 /* DMA Window Secondary Base 0 Register */ |
621 | #define PCI_HT_AM64_IDX_DMASL0 0x06 /* DMA Window Secondary Limit 0 Register */ |
621 | #define PCI_HT_AM64_IDX_DMASL0 0x06 /* DMA Window Secondary Limit 0 Register */ |
Line 636... | Line 636... | ||
636 | #define PCI_HT_DR_DATA 8 /* Data Register */ |
636 | #define PCI_HT_DR_DATA 8 /* Data Register */ |
637 | #define PCI_HT_DR_SIZEOF 12 |
637 | #define PCI_HT_DR_SIZEOF 12 |
638 | 638 | ||
639 | /* Register indices */ |
639 | /* Register indices */ |
640 | #define PCI_HT_DR_IDX_BASE_LO 0x00 /* DirectRoute Base Lower Register */ |
640 | #define PCI_HT_DR_IDX_BASE_LO 0x00 /* DirectRoute Base Lower Register */ |
641 | #define PCI_HT_DR_OTNRD 0x00000001 /* Opposite to Normal Request Direction */ |
641 | #define PCI_HT_DR_OTNRD 0x00000001 /* Opposite to Normal Request Direction */ |
642 | #define PCI_HT_DR_BL_LO 0xffffff00 /* Base/Limit Lower */ |
642 | #define PCI_HT_DR_BL_LO 0xffffff00 /* Base/Limit Lower */ |
643 | #define PCI_HT_DR_IDX_BASE_HI 0x01 /* DirectRoute Base Upper Register */ |
643 | #define PCI_HT_DR_IDX_BASE_HI 0x01 /* DirectRoute Base Upper Register */ |
644 | #define PCI_HT_DR_IDX_LIMIT_LO 0x02 /* DirectRoute Limit Lower Register */ |
644 | #define PCI_HT_DR_IDX_LIMIT_LO 0x02 /* DirectRoute Limit Lower Register */ |
645 | #define PCI_HT_DR_IDX_LIMIT_HI 0x03 /* DirectRoute Limit Upper Register */ |
645 | #define PCI_HT_DR_IDX_LIMIT_HI 0x03 /* DirectRoute Limit Upper Register */ |
646 | 646 | ||
647 | /* HyperTransport: VCSet */ |
647 | /* HyperTransport: VCSet */ |
Line 696... | Line 696... | ||
696 | #define PCI_EXP_DEVCAP_L0S 0x1c0 /* L0s Acceptable Latency */ |
696 | #define PCI_EXP_DEVCAP_L0S 0x1c0 /* L0s Acceptable Latency */ |
697 | #define PCI_EXP_DEVCAP_L1 0xe00 /* L1 Acceptable Latency */ |
697 | #define PCI_EXP_DEVCAP_L1 0xe00 /* L1 Acceptable Latency */ |
698 | #define PCI_EXP_DEVCAP_ATN_BUT 0x1000 /* Attention Button Present */ |
698 | #define PCI_EXP_DEVCAP_ATN_BUT 0x1000 /* Attention Button Present */ |
699 | #define PCI_EXP_DEVCAP_ATN_IND 0x2000 /* Attention Indicator Present */ |
699 | #define PCI_EXP_DEVCAP_ATN_IND 0x2000 /* Attention Indicator Present */ |
700 | #define PCI_EXP_DEVCAP_PWR_IND 0x4000 /* Power Indicator Present */ |
700 | #define PCI_EXP_DEVCAP_PWR_IND 0x4000 /* Power Indicator Present */ |
701 | #define PCI_EXP_DEVCAP_PWR_VAL 0x3fc0000 /* Slot Power Limit Value */ |
701 | #define PCI_EXP_DEVCAP_PWR_VAL 0x3fc0000 /* Slot Power Limit Value */ |
702 | #define PCI_EXP_DEVCAP_PWR_SCL 0xc000000 /* Slot Power Limit Scale */ |
702 | #define PCI_EXP_DEVCAP_PWR_SCL 0xc000000 /* Slot Power Limit Scale */ |
703 | #define PCI_EXP_DEVCTL 0x8 /* Device Control */ |
703 | #define PCI_EXP_DEVCTL 0x8 /* Device Control */ |
704 | #define PCI_EXP_DEVCTL_CERE 0x0001 /* Correctable Error Reporting En. */ |
704 | #define PCI_EXP_DEVCTL_CERE 0x0001 /* Correctable Error Reporting En. */ |
705 | #define PCI_EXP_DEVCTL_NFERE 0x0002 /* Non-Fatal Error Reporting Enable */ |
705 | #define PCI_EXP_DEVCTL_NFERE 0x0002 /* Non-Fatal Error Reporting Enable */ |
706 | #define PCI_EXP_DEVCTL_FERE 0x0004 /* Fatal Error Reporting Enable */ |
706 | #define PCI_EXP_DEVCTL_FERE 0x0004 /* Fatal Error Reporting Enable */ |
707 | #define PCI_EXP_DEVCTL_URRE 0x0008 /* Unsupported Request Reporting En. */ |
707 | #define PCI_EXP_DEVCTL_URRE 0x0008 /* Unsupported Request Reporting En. */ |
Line 723... | Line 723... | ||
723 | #define PCI_EXP_LNKCAP_SPEED 0x0000f /* Maximum Link Speed */ |
723 | #define PCI_EXP_LNKCAP_SPEED 0x0000f /* Maximum Link Speed */ |
724 | #define PCI_EXP_LNKCAP_WIDTH 0x003f0 /* Maximum Link Width */ |
724 | #define PCI_EXP_LNKCAP_WIDTH 0x003f0 /* Maximum Link Width */ |
725 | #define PCI_EXP_LNKCAP_ASPM 0x00c00 /* Active State Power Management */ |
725 | #define PCI_EXP_LNKCAP_ASPM 0x00c00 /* Active State Power Management */ |
726 | #define PCI_EXP_LNKCAP_L0S 0x07000 /* L0s Acceptable Latency */ |
726 | #define PCI_EXP_LNKCAP_L0S 0x07000 /* L0s Acceptable Latency */ |
727 | #define PCI_EXP_LNKCAP_L1 0x38000 /* L1 Acceptable Latency */ |
727 | #define PCI_EXP_LNKCAP_L1 0x38000 /* L1 Acceptable Latency */ |
728 | #define PCI_EXP_LNKCAP_PORT 0xff000000 /* Port Number */ |
728 | #define PCI_EXP_LNKCAP_PORT 0xff000000 /* Port Number */ |
729 | #define PCI_EXP_LNKCTL 0x10 /* Link Control */ |
729 | #define PCI_EXP_LNKCTL 0x10 /* Link Control */ |
730 | #define PCI_EXP_LNKCTL_ASPM 0x0003 /* ASPM Control */ |
730 | #define PCI_EXP_LNKCTL_ASPM 0x0003 /* ASPM Control */ |
731 | #define PCI_EXP_LNKCTL_RCB 0x0008 /* Read Completion Boundary */ |
731 | #define PCI_EXP_LNKCTL_RCB 0x0008 /* Read Completion Boundary */ |
732 | #define PCI_EXP_LNKCTL_DISABLE 0x0010 /* Link Disable */ |
732 | #define PCI_EXP_LNKCTL_DISABLE 0x0010 /* Link Disable */ |
733 | #define PCI_EXP_LNKCTL_RETRAIN 0x0020 /* Retrain Link */ |
733 | #define PCI_EXP_LNKCTL_RETRAIN 0x0020 /* Retrain Link */ |
Line 745... | Line 745... | ||
745 | #define PCI_EXP_SLTCAP_MRL 0x0004 /* MRL Sensor Present */ |
745 | #define PCI_EXP_SLTCAP_MRL 0x0004 /* MRL Sensor Present */ |
746 | #define PCI_EXP_SLTCAP_ATNI 0x0008 /* Attention Indicator Present */ |
746 | #define PCI_EXP_SLTCAP_ATNI 0x0008 /* Attention Indicator Present */ |
747 | #define PCI_EXP_SLTCAP_PWRI 0x0010 /* Power Indicator Present */ |
747 | #define PCI_EXP_SLTCAP_PWRI 0x0010 /* Power Indicator Present */ |
748 | #define PCI_EXP_SLTCAP_HPS 0x0020 /* Hot-Plug Surprise */ |
748 | #define PCI_EXP_SLTCAP_HPS 0x0020 /* Hot-Plug Surprise */ |
749 | #define PCI_EXP_SLTCAP_HPC 0x0040 /* Hot-Plug Capable */ |
749 | #define PCI_EXP_SLTCAP_HPC 0x0040 /* Hot-Plug Capable */ |
750 | #define PCI_EXP_SLTCAP_PWR_VAL 0x00007f80 /* Slot Power Limit Value */ |
750 | #define PCI_EXP_SLTCAP_PWR_VAL 0x00007f80 /* Slot Power Limit Value */ |
751 | #define PCI_EXP_SLTCAP_PWR_SCL 0x00018000 /* Slot Power Limit Scale */ |
751 | #define PCI_EXP_SLTCAP_PWR_SCL 0x00018000 /* Slot Power Limit Scale */ |
752 | #define PCI_EXP_SLTCAP_PSN 0xfff80000 /* Physical Slot Number */ |
752 | #define PCI_EXP_SLTCAP_PSN 0xfff80000 /* Physical Slot Number */ |
753 | #define PCI_EXP_SLTCTL 0x18 /* Slot Control */ |
753 | #define PCI_EXP_SLTCTL 0x18 /* Slot Control */ |
754 | #define PCI_EXP_SLTCTL_ATNB 0x0001 /* Attention Button Pressed Enable */ |
754 | #define PCI_EXP_SLTCTL_ATNB 0x0001 /* Attention Button Pressed Enable */ |
755 | #define PCI_EXP_SLTCTL_PWRF 0x0002 /* Power Fault Detected Enable */ |
755 | #define PCI_EXP_SLTCTL_PWRF 0x0002 /* Power Fault Detected Enable */ |
756 | #define PCI_EXP_SLTCTL_MRLS 0x0004 /* MRL Sensor Changed Enable */ |
756 | #define PCI_EXP_SLTCTL_MRLS 0x0004 /* MRL Sensor Changed Enable */ |
757 | #define PCI_EXP_SLTCTL_PRSD 0x0008 /* Presence Detect Changed Enable */ |
757 | #define PCI_EXP_SLTCTL_PRSD 0x0008 /* Presence Detect Changed Enable */ |
Line 823... | Line 823... | ||
823 | #define PCI_VC_RES_STATUS 26 |
823 | #define PCI_VC_RES_STATUS 26 |
824 | 824 | ||
825 | /* Power Budgeting */ |
825 | /* Power Budgeting */ |
826 | #define PCI_PWR_DSR 4 /* Data Select Register */ |
826 | #define PCI_PWR_DSR 4 /* Data Select Register */ |
827 | #define PCI_PWR_DATA 8 /* Data Register */ |
827 | #define PCI_PWR_DATA 8 /* Data Register */ |
828 | #define PCI_PWR_DATA_BASE(x) ((x) & 0xff) /* Base Power */ |
828 | #define PCI_PWR_DATA_BASE(x) ((x) & 0xff) /* Base Power */ |
829 | #define PCI_PWR_DATA_SCALE(x) (((x) >> 8) & 3) /* Data Scale */ |
829 | #define PCI_PWR_DATA_SCALE(x) (((x) >> 8) & 3) /* Data Scale */ |
830 | #define PCI_PWR_DATA_PM_SUB(x) (((x) >> 10) & 7) /* PM Sub State */ |
830 | #define PCI_PWR_DATA_PM_SUB(x) (((x) >> 10) & 7) /* PM Sub State */ |
831 | #define PCI_PWR_DATA_PM_STATE(x) (((x) >> 13) & 3) /* PM State */ |
831 | #define PCI_PWR_DATA_PM_STATE(x) (((x) >> 13) & 3) /* PM State */ |
832 | #define PCI_PWR_DATA_TYPE(x) (((x) >> 15) & 7) /* Type */ |
832 | #define PCI_PWR_DATA_TYPE(x) (((x) >> 15) & 7) /* Type */ |
833 | #define PCI_PWR_DATA_RAIL(x) (((x) >> 18) & 7) /* Power Rail */ |
833 | #define PCI_PWR_DATA_RAIL(x) (((x) >> 18) & 7) /* Power Rail */ |
834 | #define PCI_PWR_CAP 12 /* Capability */ |
834 | #define PCI_PWR_CAP 12 /* Capability */ |
835 | #define PCI_PWR_CAP_BUDGET(x) ((x) & 1) /* Included in system budget */ |
835 | #define PCI_PWR_CAP_BUDGET(x) ((x) & 1) /* Included in system budget */ |
836 | 836 | ||
837 | /* |
837 | /* |
838 | * The PCI interface treats multi-function devices as independent |
838 | * The PCI interface treats multi-function devices as independent |