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Line 36... | Line 36... | ||
36 | #define cp0_status_erl_error_bit (1<<2) |
36 | #define cp0_status_erl_error_bit (1<<2) |
37 | #define cp0_status_um_bit (1<<4) |
37 | #define cp0_status_um_bit (1<<4) |
38 | #define cp0_status_bev_bootstrap_bit (1<<22) |
38 | #define cp0_status_bev_bootstrap_bit (1<<22) |
39 | #define cp0_status_fpu_bit (1<<29) |
39 | #define cp0_status_fpu_bit (1<<29) |
40 | 40 | ||
41 | #define cp0_status_im7_shift 15 |
41 | #define cp0_status_im_shift 8 |
- | 42 | #define cp0_status_im_mask 0xff00 |
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- | 43 | ||
42 | /* |
44 | /* |
43 | * Magic value for use in msim. |
45 | * Magic value for use in msim. |
44 | * On AMD Duron 800Mhz, this roughly seems like one us. |
46 | * On AMD Duron 800Mhz, this roughly seems like one us. |
45 | */ |
47 | */ |
46 | #define cp0_compare_value 10000 |
48 | #define cp0_compare_value 10000 |
Line 61... | Line 63... | ||
61 | static inline void tlbwr(void) |
63 | static inline void tlbwr(void) |
62 | { |
64 | { |
63 | __asm__ volatile ("tlbwr"); |
65 | __asm__ volatile ("tlbwr"); |
64 | } |
66 | } |
65 | 67 | ||
- | 68 | #define cp0_mask_all_int() cp0_status_write(cp0_status_read() & ~(cp0_status_im_mask)) |
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- | 69 | #define cp0_unmask_all_int() cp0_status_write(cp0_status_read() | cp0_status_im_mask) |
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- | 70 | #define cp0_mask_int(it) cp0_status_write(cp0_status_read() & ~(1<<(cp0_status_im_shift+(it)))) |
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- | 71 | #define cp0_unmask_int(it) cp0_status_write(cp0_status_read() | (1<<(cp0_status_im_shift+(it)))) |
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66 | 72 | ||
67 | 73 | ||
68 | extern __u32 cp0_index_read(void); |
74 | extern __u32 cp0_index_read(void); |
69 | extern void cp0_idnex_write(__u32 val); |
75 | extern void cp0_idnex_write(__u32 val); |
70 | 76 |