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39 | #define cp0_status_fpu_bit (1<<29) |
39 | #define cp0_status_fpu_bit (1<<29) |
40 | 40 | ||
41 | #define cp0_status_im_shift 8 |
41 | #define cp0_status_im_shift 8 |
42 | #define cp0_status_im_mask 0xff00 |
42 | #define cp0_status_im_mask 0xff00 |
43 | 43 | ||
- | 44 | #define cp0_cause_excno(cause) ((cause >> 2) & 0x1f) |
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- | 45 | #define cp0_cause_coperr(cause) ((cause >> 28) & 0x3) |
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- | 46 | ||
- | 47 | #define fpu_cop_id 1 |
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- | 48 | ||
44 | /* |
49 | /* |
45 | * Magic value for use in msim. |
50 | * Magic value for use in msim. |
46 | * On AMD Duron 800Mhz, this roughly seems like one us. |
51 | * On AMD Duron 800Mhz, this roughly seems like one us. |
47 | */ |
52 | */ |
48 | #define cp0_compare_value 10000 |
53 | #define cp0_compare_value 10000 |