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Rev 2927 | Rev 3674 | ||
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Line 473... | Line 473... | ||
473 | panic("%s: va=%p, rid=%d, iip=%p\n", __func__, va, rid, istate->cr_iip); |
473 | panic("%s: va=%p, rid=%d, iip=%p\n", __func__, va, rid, istate->cr_iip); |
474 | } |
474 | } |
475 | } |
475 | } |
476 | } |
476 | } |
477 | 477 | ||
- | 478 | ||
- | 479 | ||
- | 480 | static int is_io_page_accessible(int page) |
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- | 481 | { |
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- | 482 | if(TASK->arch.iomap) return bitmap_get(TASK->arch.iomap,page); |
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- | 483 | else return 0; |
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- | 484 | } |
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- | 485 | ||
- | 486 | #define IO_FRAME_BASE 0xFFFFC000000 |
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- | 487 | ||
- | 488 | /** There is special handling of memmaped lagacy io, because |
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- | 489 | * of 4KB sized access |
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- | 490 | * only for userspace |
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- | 491 | * |
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- | 492 | * @param va virtual address of page fault |
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- | 493 | * @param istate Structure with saved interruption state. |
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- | 494 | * |
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- | 495 | * |
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- | 496 | * @return 1 on success, 0 on fail |
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- | 497 | */ |
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- | 498 | static int try_memmap_io_insertion(uintptr_t va, istate_t *istate) |
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- | 499 | { |
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- | 500 | if((va >= IO_OFFSET ) && (va < IO_OFFSET + (1<<IO_PAGE_WIDTH))) |
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- | 501 | if(TASK){ |
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- | 502 | ||
- | 503 | uint64_t io_page=(va & ((1<<IO_PAGE_WIDTH)-1)) >> (USPACE_IO_PAGE_WIDTH); |
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- | 504 | if(is_io_page_accessible(io_page)){ |
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- | 505 | //printf("Insert %llX\n",va); |
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- | 506 | ||
- | 507 | uint64_t page,frame; |
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- | 508 | ||
- | 509 | page = IO_OFFSET + (1 << USPACE_IO_PAGE_WIDTH) * io_page; |
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- | 510 | frame = IO_FRAME_BASE + (1 << USPACE_IO_PAGE_WIDTH) * io_page; |
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- | 511 | ||
- | 512 | ||
- | 513 | tlb_entry_t entry; |
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- | 514 | ||
- | 515 | entry.word[0] = 0; |
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- | 516 | entry.word[1] = 0; |
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- | 517 | ||
- | 518 | entry.p = true; /* present */ |
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- | 519 | entry.ma = MA_UNCACHEABLE; |
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- | 520 | entry.a = true; /* already accessed */ |
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- | 521 | entry.d = true; /* already dirty */ |
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- | 522 | entry.pl = PL_USER; |
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- | 523 | entry.ar = AR_READ | AR_WRITE; |
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- | 524 | entry.ppn = frame >> PPN_SHIFT; //MUSIM spocitat frame |
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- | 525 | entry.ps = USPACE_IO_PAGE_WIDTH; |
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- | 526 | ||
- | 527 | dtc_mapping_insert(page, TASK->as->asid, entry); //Musim zjistit ASID |
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- | 528 | return 1; |
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- | 529 | }else { |
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- | 530 | fault_if_from_uspace(istate,"IO access fault at %p",va); |
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- | 531 | return 0; |
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- | 532 | } |
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- | 533 | } else |
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- | 534 | return 0; |
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- | 535 | else |
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- | 536 | return 0; |
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- | 537 | ||
- | 538 | return 0; |
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- | 539 | ||
- | 540 | } |
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- | 541 | ||
- | 542 | ||
- | 543 | ||
- | 544 | ||
478 | /** Data TLB fault handler for faults with VHPT turned off. |
545 | /** Data TLB fault handler for faults with VHPT turned off. |
479 | * |
546 | * |
480 | * @param vector Interruption vector. |
547 | * @param vector Interruption vector. |
481 | * @param istate Structure with saved interruption state. |
548 | * @param istate Structure with saved interruption state. |
482 | */ |
549 | */ |
Line 509... | Line 576... | ||
509 | * Insert it into data translation cache. |
576 | * Insert it into data translation cache. |
510 | */ |
577 | */ |
511 | dtc_pte_copy(t); |
578 | dtc_pte_copy(t); |
512 | page_table_unlock(AS, true); |
579 | page_table_unlock(AS, true); |
513 | } else { |
580 | } else { |
- | 581 | page_table_unlock(AS, true); |
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- | 582 | if (try_memmap_io_insertion(va,istate)) return; |
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514 | /* |
583 | /* |
515 | * Forward the page fault to the address space page fault handler. |
584 | * Forward the page fault to the address space page fault handler. |
516 | */ |
585 | */ |
517 | page_table_unlock(AS, true); |
- | |
518 | if (as_page_fault(va, PF_ACCESS_READ, istate) == AS_PF_FAULT) { |
586 | if (as_page_fault(va, PF_ACCESS_READ, istate) == AS_PF_FAULT) { |
519 | fault_if_from_uspace(istate,"Page fault at %p",va); |
587 | fault_if_from_uspace(istate,"Page fault at %p",va); |
520 | panic("%s: va=%p, rid=%d, iip=%p\n", __func__, va, rid, istate->cr_iip); |
588 | panic("%s: va=%p, rid=%d, iip=%p\n", __func__, va, rid, istate->cr_iip); |
521 | } |
589 | } |
522 | } |
590 | } |