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#include <arch/machine.h>
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#include <arch/machine.h>
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#include <arch/mm/page_fault.h>
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#include <arch/mm/page_fault.h>
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#include <print.h>
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#include <print.h>
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#include <syscall/syscall.h>
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#include <syscall/syscall.h>
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- 
 
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/** Offset used in calculation of exception handler's relative address.
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 *
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 * @see install_handler()
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 */
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#define PREFETCH_OFFSET      0x8
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#define PREFETCH_OFFSET      0x8
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#define BRANCH_OPCODE        0xea000000
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/** LDR instruction's code */
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#define LDR_OPCODE           0xe59ff000
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#define LDR_OPCODE           0xe59ff000
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#define VALID_BRANCH_MASK    0xff000000
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#define EXC_VECTORS_SIZE     0x20
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#define EXC_VECTORS          0x8
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/** Number of exception vectors. */
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#define EXC_VECTORS          8
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/** Size of memory block occupied by exception vectors. */
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#define EXC_VECTORS_SIZE     (EXC_VECTORS * 4)
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/** Kernel stack pointer.
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 *
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 * It is set when thread switches to user mode,
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 * and then used for exception handling.
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 */
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extern uintptr_t supervisor_sp;
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extern uintptr_t supervisor_sp;
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/** Temporary exception stack pointer.
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 *
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 * Temporary stack is used in exceptions handling routines
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 * before switching to thread's kernel stack.
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 */
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extern uintptr_t exc_stack;
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extern uintptr_t exc_stack;
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/** Switches to kernel stack and saves all registers there.
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/** Switches to kernel stack and saves all registers there.
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 *
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 *
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 * Temporary exception stack is used to save a few registers
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 * Temporary exception stack is used to save a few registers
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 * before stack switch takes place.
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 * before stack switch takes place.
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 */
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 */
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    mov r13, r1             \n\
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    mov r13, r1             \n\
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2:"
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2:"
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);
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);
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}
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}
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- 
 
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/** Returns from exception mode.
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/** Returns from exception mode.
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 *
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 *
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 * Previously saved state of registers (including control register)
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 * Previously saved state of registers (including control register)
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 * is restored from the stack.
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 * is restored from the stack.
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 */
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 */
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    @actual return              \n\
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    @actual return              \n\
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4:  ldmfd r13, {r0-r12, pc}^"
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4:  ldmfd r13, {r0-r12, pc}^"
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);
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);
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}
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}
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/** Switch CPU to mode in which interrupts are serviced (currently it
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 * is Undefined mode).
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 *
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 * The default mode for interrupt servicing (Interrupt Mode)
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 * can not be used because of nested interrupts (which can occur
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 * because interrupt are enabled in higher levels of interrupt handler).
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 */
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inline static void switchToIrqServicingMode()
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{
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    /* switch to Undefined mode */
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    asm volatile(
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        /* save regs used during switching */
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        "stmfd sp!, {r0-r3}     \n"
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        /* save stack pointer and link register to r1, r2 */
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        "mov r1, sp         \n"
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        "mov r2, lr         \n"
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        /* mode switch */
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        "mrs r0, cpsr           \n"
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        "bic r0, r0, #0x1f      \n"
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        "orr r0, r0, #0x1b      \n"
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        "msr cpsr_c, r0         \n"
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        /* restore saved sp and lr */
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        "mov sp, r1         \n"
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        "mov lr, r2         \n"
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        /* restore original regs */
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        "ldmfd sp!, {r0-r3}     \n"
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    );
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}
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/** Calls exception dispatch routine. */
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/** Calls exception dispatch routine. */
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#define CALL_EXC_DISPATCH(exception)        \
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#define CALL_EXC_DISPATCH(exception)        \
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    asm("mov r0, %0" : : "i" (exception));  \
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    asm("mov r0, %0" : : "i" (exception));  \
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    asm("mov r1, r13");         \
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    asm("mov r1, r13");         \
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    asm("bl exc_dispatch");    
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    asm("bl exc_dispatch");    
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/** General exception handler.
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/** General exception handler.
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 *
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 *
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 *  Stores registers, dispatches the exception,
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 *  Stores registers, dispatches the exception,
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 *  and finally restores registers and returns from exception processing.
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 *  and finally restores registers and returns from exception processing.
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 *
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 *
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 */
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 */
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static void irq_exception_entry()
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static void irq_exception_entry()
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{
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{
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    asm("sub lr, lr, #4");
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    asm("sub lr, lr, #4");
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    setup_stack_and_save_regs();
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    setup_stack_and_save_regs();
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    /* switch to Undefined mode */
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    switchToIrqServicingMode();
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    asm("stmfd sp!, {r0-r3}");
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    asm("mov r1, sp");
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    asm("mov r2, lr");
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    asm("mrs r0, cpsr");
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    asm("bic r0, r0, #0x1f");
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    asm("orr r0, r0, #0x1b");
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    asm("msr cpsr_c, r0");
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    asm("mov sp, r1");
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    asm("mov lr, r2");
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    asm("ldmfd sp!, {r0-r3}");
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    CALL_EXC_DISPATCH(EXC_IRQ)
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    CALL_EXC_DISPATCH(EXC_IRQ)
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260 
    load_regs();
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    load_regs();
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}
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}
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