Rev 2326 | Go to most recent revision | Show entire file | Ignore whitespace | Details | Blame | Last modification | View Log | RSS feed
Rev 2326 | Rev 2340 | ||
---|---|---|---|
Line 42... | Line 42... | ||
42 | #include <ddi/device.h> |
42 | #include <ddi/device.h> |
43 | #include <mm/page.h> |
43 | #include <mm/page.h> |
44 | #include <arch/machine.h> |
44 | #include <arch/machine.h> |
45 | #include <arch/debug/print.h> |
45 | #include <arch/debug/print.h> |
46 | 46 | ||
- | 47 | ||
47 | /** Address of devices. */ |
48 | /** Address of devices. */ |
48 | #define GXEMUL_VIDEORAM 0x10000000 |
49 | #define GXEMUL_VIDEORAM 0x10000000 |
49 | #define GXEMUL_KBD 0x10000000 |
50 | #define GXEMUL_KBD 0x10000000 |
50 | #define GXEMUL_HALT_OFFSET 0x10 |
51 | #define GXEMUL_HALT_OFFSET 0x10 |
51 | #define GXEMUL_RTC 0x15000000 |
52 | #define GXEMUL_RTC 0x15000000 |
Line 54... | Line 55... | ||
54 | #define GXEMUL_IRQC 0x16000000 |
55 | #define GXEMUL_IRQC 0x16000000 |
55 | #define GXEMUL_IRQC_MASK_OFFSET 0x4 |
56 | #define GXEMUL_IRQC_MASK_OFFSET 0x4 |
56 | #define GXEMUL_IRQC_UNMASK_OFFSET 0x8 |
57 | #define GXEMUL_IRQC_UNMASK_OFFSET 0x8 |
57 | #define GXEMUL_MP 0x11000000 |
58 | #define GXEMUL_MP 0x11000000 |
58 | #define GXEMUL_MP_MEMSIZE_OFFSET 0x0090 |
59 | #define GXEMUL_MP_MEMSIZE_OFFSET 0x0090 |
- | 60 | #define GXEMUL_FB 0x12000000 |
|
59 | 61 | ||
60 | 62 | ||
61 | /** IRQs */ |
63 | /** IRQs */ |
62 | #define GXEMUL_KBD_IRQ 2 |
64 | #define GXEMUL_KBD_IRQ 2 |
63 | #define GXEMUL_TIMER_IRQ 4 |
65 | #define GXEMUL_TIMER_IRQ 4 |
Line 79... | Line 81... | ||
79 | .suspend = gxemul_disable, |
81 | .suspend = gxemul_disable, |
80 | .write = gxemul_write, |
82 | .write = gxemul_write, |
81 | .read = gxemul_do_read, |
83 | .read = gxemul_do_read, |
82 | }; |
84 | }; |
83 | 85 | ||
- | 86 | /** Return the mask of active interrupts. */ |
|
- | 87 | static inline uint32_t gxemul_irqc_get_sources(void) |
|
- | 88 | { |
|
- | 89 | return *(uint32_t*) gxemul_hw_map.irqc; |
|
- | 90 | } |
|
- | 91 | ||
- | 92 | /** Masks interrupt. |
|
- | 93 | * |
|
- | 94 | * @param irq interrupt number |
|
- | 95 | */ |
|
- | 96 | static inline void gxemul_irqc_mask(uint32_t irq) |
|
- | 97 | { |
|
- | 98 | *(uint32_t*) gxemul_hw_map.irqc_mask = irq; |
|
- | 99 | } |
|
- | 100 | ||
- | 101 | /** Unmasks interrupt. |
|
- | 102 | * |
|
- | 103 | * @param irq interrupt number |
|
- | 104 | */ |
|
- | 105 | static inline void gxemul_irqc_unmask(uint32_t irq) |
|
- | 106 | { |
|
- | 107 | *(uint32_t*) gxemul_hw_map.irqc_unmask = irq; |
|
- | 108 | } |
|
84 | 109 | ||
85 | /** Initializes #gxemul_hw_map. */ |
110 | /** Initializes #gxemul_hw_map. */ |
86 | void machine_hw_map_init(void) |
111 | void machine_hw_map_init(void) |
87 | { |
112 | { |
88 | gxemul_hw_map.videoram = hw_map(GXEMUL_VIDEORAM, PAGE_SIZE); |
113 | gxemul_hw_map.videoram = hw_map(GXEMUL_VIDEORAM, PAGE_SIZE); |
Line 97... | Line 122... | ||
97 | 122 | ||
98 | hw_map_init_called = true; |
123 | hw_map_init_called = true; |
99 | } |
124 | } |
100 | 125 | ||
101 | /** Putchar that works with gxemul */ |
126 | /** Putchar that works with gxemul */ |
102 | void gxemul_write(chardev_t *dev, const char ch) |
127 | static void gxemul_write(chardev_t *dev, const char ch) |
103 | { |
128 | { |
104 | *((char *) gxemul_hw_map.videoram) = ch; |
129 | *((char *) gxemul_hw_map.videoram) = ch; |
105 | } |
130 | } |
106 | 131 | ||
107 | /* Called from getc(). */ |
132 | /* Called from getc(). */ |
108 | void gxemul_enable(chardev_t *dev) |
133 | static void gxemul_enable(chardev_t *dev) |
109 | { |
134 | { |
110 | // cp0_unmask_int(GXEMUL_KBD_IRQ); |
- | |
111 | gxemul_irqc_unmask(GXEMUL_KBD_IRQ); |
135 | gxemul_irqc_unmask(GXEMUL_KBD_IRQ); |
112 | } |
136 | } |
113 | 137 | ||
114 | /* Called from getc(). */ |
138 | /* Called from getc(). */ |
115 | void gxemul_disable(chardev_t *dev) |
139 | static void gxemul_disable(chardev_t *dev) |
116 | { |
140 | { |
117 | // cp0_mask_int(GXEMUL_KBD_IRQ); |
- | |
118 | gxemul_irqc_mask(GXEMUL_KBD_IRQ); |
141 | gxemul_irqc_mask(GXEMUL_KBD_IRQ); |
119 | } |
142 | } |
120 | 143 | ||
121 | /** Read character using polling, assume interrupts disabled */ |
144 | /** Read character using polling, assume interrupts disabled */ |
122 | static char gxemul_do_read(chardev_t *dev) |
145 | static char gxemul_do_read(chardev_t *dev) |
Line 189... | Line 212... | ||
189 | gxemul_irq.inr = GXEMUL_KBD_IRQ; |
212 | gxemul_irq.inr = GXEMUL_KBD_IRQ; |
190 | gxemul_irq.claim = gxemul_claim; |
213 | gxemul_irq.claim = gxemul_claim; |
191 | gxemul_irq.handler = gxemul_irq_handler; |
214 | gxemul_irq.handler = gxemul_irq_handler; |
192 | irq_register(&gxemul_irq); |
215 | irq_register(&gxemul_irq); |
193 | 216 | ||
194 | // cp0_unmask_int(GXEMUL_KBD_IRQ); |
- | |
195 | gxemul_irqc_unmask(GXEMUL_KBD_IRQ); |
217 | gxemul_irqc_unmask(GXEMUL_KBD_IRQ); |
196 | 218 | ||
197 | sysinfo_set_item_val("kbd", NULL, true); |
219 | sysinfo_set_item_val("kbd", NULL, true); |
198 | sysinfo_set_item_val("kbd.devno", NULL, devno); |
220 | sysinfo_set_item_val("kbd.devno", NULL, devno); |
199 | sysinfo_set_item_val("kbd.inr", NULL, GXEMUL_KBD_IRQ); |
221 | sysinfo_set_item_val("kbd.inr", NULL, GXEMUL_KBD_IRQ); |
200 | sysinfo_set_item_val("kbd.address.virtual", NULL, gxemul_hw_map.kbd); |
222 | sysinfo_set_item_val("kbd.address.virtual", NULL, gxemul_hw_map.kbd); |
201 | } |
223 | } |
202 | 224 | ||
203 | /** Return the mask of active interrupts. */ |
- | |
204 | inline uint32_t gxemul_irqc_get_sources(void) |
- | |
205 | { |
- | |
206 | return *(uint32_t*) gxemul_hw_map.irqc; |
- | |
207 | } |
- | |
208 | - | ||
209 | /** Masks interrupt. |
- | |
210 | * |
- | |
211 | * @param irq interrupt number |
- | |
212 | */ |
- | |
213 | inline void gxemul_irqc_mask(uint32_t irq) |
- | |
214 | { |
- | |
215 | *(uint32_t*) gxemul_hw_map.irqc_mask = irq; |
- | |
216 | } |
- | |
217 | - | ||
218 | /** Unmasks interrupt. |
- | |
219 | * |
- | |
220 | * @param irq interrupt number |
- | |
221 | */ |
- | |
222 | inline void gxemul_irqc_unmask(uint32_t irq) |
- | |
223 | { |
- | |
224 | *(uint32_t*) gxemul_hw_map.irqc_unmask = irq; |
- | |
225 | } |
- | |
226 | 225 | ||
227 | 226 | ||
228 | /** Starts gxemul Real Time Clock device, which asserts regular interrupts. |
227 | /** Starts gxemul Real Time Clock device, which asserts regular interrupts. |
229 | * |
228 | * |
230 | * @param frequency interrupts frequency (0 disables RTC) |
229 | * @param frequency interrupts frequency (0 disables RTC) |
231 | */ |
230 | */ |
232 | void gxemul_timer_start(uint32_t frequency) |
231 | static void gxemul_timer_start(uint32_t frequency) |
233 | { |
232 | { |
234 | *(uint32_t*) gxemul_hw_map.rtc_freq = frequency; |
233 | *(uint32_t*) gxemul_hw_map.rtc_freq = frequency; |
235 | } |
234 | } |
236 | 235 | ||
237 | static irq_ownership_t gxemul_timer_claim(void) |
236 | static irq_ownership_t gxemul_timer_claim(void) |
Line 271... | Line 270... | ||
271 | } |
270 | } |
272 | 271 | ||
273 | /** |
272 | /** |
274 | * Initializes and registers timer interrupt handler. |
273 | * Initializes and registers timer interrupt handler. |
275 | */ |
274 | */ |
276 | void gxemul_timer_irq_init() |
275 | static void gxemul_timer_irq_init() |
277 | { |
276 | { |
278 | irq_initialize(&gxemul_timer_irq); |
277 | irq_initialize(&gxemul_timer_irq); |
279 | gxemul_timer_irq.devno = device_assign_devno(); |
278 | gxemul_timer_irq.devno = device_assign_devno(); |
280 | gxemul_timer_irq.inr = GXEMUL_TIMER_IRQ; |
279 | gxemul_timer_irq.inr = GXEMUL_TIMER_IRQ; |
281 | gxemul_timer_irq.claim = gxemul_timer_claim; |
280 | gxemul_timer_irq.claim = gxemul_timer_claim; |
Line 319... | Line 318... | ||
319 | *(addr + GXEMUL_HALT_OFFSET) = '\0'; |
318 | *(addr + GXEMUL_HALT_OFFSET) = '\0'; |
320 | } |
319 | } |
321 | 320 | ||
322 | void machine_irq_exception(int exc_no, istate_t *istate) |
321 | void machine_irq_exception(int exc_no, istate_t *istate) |
323 | { |
322 | { |
- | 323 | /* switch to Undefined mode */ |
|
- | 324 | /* |
|
- | 325 | asm volatile( |
|
- | 326 | "stmfd sp!, {r0-r3}\n" |
|
- | 327 | "mov r1, sp\n" |
|
- | 328 | "mov r2, lr\n" |
|
- | 329 | "mrs r3, spsr\n" |
|
- | 330 | "mrs r0, cpsr\n" |
|
- | 331 | "bic r0, r0, #0x1f\n" |
|
- | 332 | "orr r0, r0, #0x1b\n" |
|
- | 333 | "msr cpsr_c, r0\n" |
|
- | 334 | "mov sp, r1\n" |
|
- | 335 | "mov lr, r2\n" |
|
- | 336 | "msr spsr, r3\n" |
|
- | 337 | "ldmfd sp!, {r0-r3}\n" |
|
- | 338 | ); |
|
- | 339 | */ |
|
- | 340 | ||
324 | uint32_t sources = gxemul_irqc_get_sources(); |
341 | uint32_t sources = gxemul_irqc_get_sources(); |
325 | int i = 0; |
342 | int i = 0; |
326 | for (; i < GXEMUL_IRQC_MAX_IRQ; i++) { |
343 | for (; i < GXEMUL_IRQC_MAX_IRQ; i++) { |
327 | if (sources & (1 << i)) { |
344 | if (sources & (1 << i)) { |
328 | irq_t *irq = irq_dispatch_and_lock(i); |
345 | irq_t *irq = irq_dispatch_and_lock(i); |
Line 358... | Line 375... | ||
358 | 375 | ||
359 | if (noirq) |
376 | if (noirq) |
360 | aux_puts("IRQ exception without source\n");*/ |
377 | aux_puts("IRQ exception without source\n");*/ |
361 | } |
378 | } |
362 | 379 | ||
- | 380 | ||
363 | /** @} |
381 | /** @} |
364 | */ |
382 | */ |