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 */
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 */
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#include <arch/pm.h>
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#include <arch/pm.h>
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#include <arch/mm/page.h>
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#include <arch/mm/page.h>
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#include <arch/types.h>
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#include <arch/types.h>
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#include <arch/interrupt.h>
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#include <arch/asm.h>
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#include <config.h>
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#include <memstr.h>
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#include <mm/heap.h>
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#include <debug.h>
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/*
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/*
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 * There is no segmentation in long mode so we set up flat mode. In this
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 * There is no segmentation in long mode so we set up flat mode. In this
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 * mode, we use, for each privilege level, two segments spanning the
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 * mode, we use, for each privilege level, two segments spanning the
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 * whole memory. One is for code and one is for data.
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 * whole memory. One is for code and one is for data.
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      .access      = AR_PRESENT | AR_CODE | DPL_USER,
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      .access      = AR_PRESENT | AR_CODE | DPL_USER,
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      .limit_16_19 = 0xf,
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      .limit_16_19 = 0xf,
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      .available   = 0,
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      .available   = 0,
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      .longmode    = 1,
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      .longmode    = 1,
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      .special     = 0,
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      .special     = 0,
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      .granularity = 0,
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      .granularity = 1,
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      .base_24_31  = 0 },
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      .base_24_31  = 0 },
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    /* UDATA descriptor */
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    /* UDATA descriptor */
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    { .limit_0_15  = 0xffff,
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    { .limit_0_15  = 0xffff,
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      .base_0_15   = 0,
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      .base_0_15   = 0,
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      .base_16_23  = 0,
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      .base_16_23  = 0,
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      .available   = 0,
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      .available   = 0,
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      .longmode    = 0,
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      .longmode    = 0,
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      .special     = 0,
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      .special     = 0,
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      .granularity = 1,
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      .granularity = 1,
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      .base_24_31  = 0 },
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      .base_24_31  = 0 },
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    /* TSS descriptor - set up will be completed later */
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    /* TSS descriptor - set up will be completed later,
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     * on AMD64 it is 64-bit - 2 items in table */
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    { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
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    { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }
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    { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }
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};
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};
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struct ptr_16_64 gdtr = {.limit = sizeof(gdtr), .base= (__u64) &gdtr };
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struct idescriptor idt[IDT_ITEMS];
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struct idescriptor idt[IDT_ITEMS];
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static struct tss tss;
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static struct tss tss;
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/* Does not compile correctly if it does not exist */
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/* TODO: Does not compile correctly if it does not exist ???? */
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int __attribute__ ((section ("K_DATA_START"))) __fake;
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int __attribute__ ((section ("K_DATA_START"))) __fake;
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void gdt_tss_setbase(struct descriptor *d, __address base)
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{
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    struct tss_descriptor *td = (struct tss_descriptor *) d;
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    td->base_0_15 = base & 0xffff;
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    td->base_16_23 = ((base) >> 16) & 0xff;
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    td->base_24_31 = ((base) >> 24) & 0xff;
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    td->base_32_63 = ((base) >> 32);
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}
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void gdt_tss_setlimit(struct descriptor *d, __u32 limit)
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{
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    struct tss_descriptor *td = (struct tss_descriptor *) d;
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    td->limit_0_15 = limit & 0xffff;
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    td->limit_16_19 = (limit >> 16) & 0xf;
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}
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void idt_setoffset(struct idescriptor *d, __address offset)
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{
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    /*
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     * Offset is a linear address.
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     */
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    d->offset_0_15 = offset & 0xffff;
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    d->offset_16_31 = offset >> 16 & 0xffff;
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    d->offset_32_63 = offset >> 32;
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}
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void tss_initialize(struct tss *t)
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{
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    memsetb((__address) t, sizeof(struct tss), 0);
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}
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/*
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 * This function takes care of proper setup of IDT and IDTR.
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 155 
 */
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 156 
void idt_init(void)
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{
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    struct idescriptor *d;
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    int i;
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    for (i = 0; i < IDT_ITEMS; i++) {
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        d = &idt[i];
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        d->unused = 0;
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        d->selector = idtselector(KTEXT_DES);
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        d->present = 1;
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        d->type = AR_INTERRUPT; /* masking interrupt */
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        if (i == VECTOR_SYSCALL) {
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            /*
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             * The syscall interrupt gate must be calleable from userland.
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             */
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            d->dpl |= PL_USER;
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 175 
        }
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        idt_setoffset(d, ((__address) interrupt_handlers) + i*interrupt_handler_size);
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        trap_register(i, null_interrupt);
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 179 
    }
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 180 
    trap_register(13, gp_fault);
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 181 
    trap_register( 7, nm_fault);
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 182 
    trap_register(12, ss_fault);
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 183 
}
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/* Clean IOPL(12,13) and NT(14) flags in EFLAGS register */
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 187 
static void clean_IOPL_NT_flags(void)
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 188 
{
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 189 
    asm
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    (
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 191 
        "pushfq;"
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        "pop %%rax;"
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        "and $~(0x7000),%%rax;"
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        "pushq %%rax;"
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        "popfq;"
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        :
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 197 
        :
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 198 
        :"%rax"
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 199 
    );
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 200 
}
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 201 
 
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 202 
/* Clean AM(18) flag in CR0 register */
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 203 
static void clean_AM_flag(void)
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 204 
{
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 205 
    asm
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 206 
    (
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        "mov %%cr0,%%rax;"
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        "and $~(0x40000),%%rax;"
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        "mov %%rax,%%cr0;"
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        :
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 211 
        :
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 212 
        :"%rax"
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    );
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 214 
}
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 215 
 
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void pm_init(void)
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 217 
{
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 218 
    struct descriptor *gdt_p = (struct descriptor *) PA2KA(gdtr.base);
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 219 
    struct tss_descriptor *tss_d;
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 221 
    /*
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 222 
     * Each CPU has its private GDT and TSS.
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     * All CPUs share one IDT.
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 224 
     */
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 225 
 
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    if (config.cpu_active == 1) {
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 227 
        idt_init();
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 228 
        /*
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 229 
         * NOTE: bootstrap CPU has statically allocated TSS, because
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 230 
         * the heap hasn't been initialized so far.
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 231 
         */
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 232 
        tss_p = &tss;
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 233 
    }
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 234 
    else {
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 235 
        tss_p = (struct tss *) malloc(sizeof(struct tss));
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 236 
        if (!tss_p)
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 237 
            panic("could not allocate TSS\n");
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 238 
    }
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 239 
 
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 240 
    tss_initialize(tss_p);
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 241 
 
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 242 
    tss_d = (struct tss_descriptor *) &gdt_p[TSS_DES];
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 243 
    tss_d[TSS_DES].present = 1;
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 244 
    tss_d[TSS_DES].type = AR_TSS;
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 245 
    tss_d[TSS_DES].dpl = PL_KERNEL;
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 246 
   
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 247 
    gdt_tss_setbase(&gdt_p[TSS_DES], (__address) tss_p);
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 248 
    gdt_tss_setlimit(&gdt_p[TSS_DES], sizeof(struct tss) - 1);
- 
 
 249 
 
- 
 
 250 
    /*
- 
 
 251 
     * As of this moment, the current CPU has its own GDT pointing
- 
 
 252 
     * to its own TSS. We just need to load the TR register.
- 
 
 253 
     */
- 
 
 254 
    __asm__("ltr %0" : : "r" ((__u16) gdtselector(TSS_DES)));
- 
 
 255 
   
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 256 
    clean_IOPL_NT_flags();    /* Disable I/O on nonprivileged levels */
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 257 
    clean_AM_flag();          /* Disable alignment check */
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 258 
}