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Rev 3403 Rev 3674
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	/*
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	/*
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	 * We have copied code and now we need to guarantee cache coherence.
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	 * We have copied code and now we need to guarantee cache coherence.
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	 * 1. Make sure that the code we have moved has drained to main memory.
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	 * 1. Make sure that the code we have moved has drained to main memory.
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	 * 2. Invalidate I-cache.
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	 * 2. Invalidate I-cache.
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	 * 3. Flush instruction pipeline.
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	 * 3. Flush instruction pipeline.
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	 */
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	 */
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	/*
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	 * US3 processors have a write-invalidate cache, so explicitly
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	 * invalidating it is not required. Whether to invalidate I-cache
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	 * or not is decided according to the value of the global
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	 * "subarchitecture" variable (set in the bootstrap).
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	 */
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	set subarchitecture, %g2
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	ldub [%g2], %g2
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	cmp %g2, 3
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	be 1f
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	nop
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0:
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	call	icache_flush
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	call icache_flush
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	nop
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1:
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	membar	#StoreStore
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	membar #StoreStore
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	/*
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	 * Flush the instruction pipeline.
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	 */
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	flush	%i7
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	flush	%i7
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	mov %o0, %l1
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	mov %o0, %l1
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	mov %o1, %o0
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	mov %o1, %o0
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	mov %o2, %o1
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	mov %o2, %o1
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	stxa	%g0, [%g1] ASI_ICACHE_TAG
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	stxa	%g0, [%g1] ASI_ICACHE_TAG
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	membar	#Sync
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	membar	#Sync
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	retl
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	retl
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	! SF Erratum #51
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	! SF Erratum #51
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	nop
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	nop
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.global ofw
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.global ofw
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ofw:
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ofw:
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	save %sp, -STACK_WINDOW_SAVE_AREA_SIZE, %sp
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	save %sp, -STACK_WINDOW_SAVE_AREA_SIZE, %sp
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	set ofw_cif, %l0
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	set ofw_cif, %l0
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	ldx [%l0], %l0
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	ldx [%l0], %l0