Subversion Repositories HelenOS

Rev

Rev 3022 | Go to most recent revision | Show entire file | Ignore whitespace | Details | Blame | Last modification | View Log | RSS feed

Rev 3022 Rev 4055
Line 25... Line 25...
25
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
25
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26
# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26
# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27
#
27
#
28
 
28
 
29
#include <arch/arch.h>
29
#include <arch/arch.h>
-
 
30
#include <arch/cpu.h>
30
#include <arch/regdef.h>
31
#include <arch/regdef.h>
31
#include <arch/boot/boot.h>
32
#include <arch/boot/boot.h>
32
#include <arch/stack.h>
33
#include <arch/stack.h>
33
 
34
 
34
#include <arch/mm/mmu.h>
35
#include <arch/mm/mmu.h>
Line 45... Line 46...
45
.section K_TEXT_START, "ax"
46
.section K_TEXT_START, "ax"
46
 
47
 
47
#define BSP_FLAG	1
48
#define BSP_FLAG	1
48
 
49
 
49
/*
50
/*
-
 
51
 * 2^PHYSMEM_ADDR_SIZE is the size of the physical address space on
-
 
52
 * a given processor.
-
 
53
 */
-
 
54
#if defined (US)
-
 
55
    #define PHYSMEM_ADDR_SIZE	41
-
 
56
#elif defined (US3)
-
 
57
    #define PHYSMEM_ADDR_SIZE	43
-
 
58
#endif
-
 
59
 
-
 
60
/*
50
 * Here is where the kernel is passed control from the boot loader.
61
 * Here is where the kernel is passed control from the boot loader.
51
 * 
62
 * 
52
 * The registers are expected to be in this state:
63
 * The registers are expected to be in this state:
53
 * - %o0 starting address of physical memory + bootstrap processor flag
64
 * - %o0 starting address of physical memory + bootstrap processor flag
54
 * 	bits 63...1:	physical memory starting address / 2
65
 * 	bits 63...1:	physical memory starting address / 2
Line 65... Line 76...
65
kernel_image_start:
76
kernel_image_start:
66
	mov BSP_FLAG, %l0
77
	mov BSP_FLAG, %l0
67
	and %o0, %l0, %l7			! l7 <= bootstrap processor?
78
	and %o0, %l0, %l7			! l7 <= bootstrap processor?
68
	andn %o0, %l0, %l6			! l6 <= start of physical memory
79
	andn %o0, %l0, %l6			! l6 <= start of physical memory
69
 
80
 
70
	! Get bits 40:13 of physmem_base.
81
	! Get bits (PHYSMEM_ADDR_SIZE - 1):13 of physmem_base.
71
	srlx %l6, 13, %l5
82
	srlx %l6, 13, %l5
-
 
83
	
-
 
84
	! l5 <= physmem_base[(PHYSMEM_ADDR_SIZE - 1):13]
72
	sllx %l5, 13 + (63 - 40), %l5
85
	sllx %l5, 13 + (63 - (PHYSMEM_ADDR_SIZE - 1)), %l5
73
	srlx %l5, 63 - 40, %l5			! l5 <= physmem_base[40:13]
86
	srlx %l5, 63 - (PHYSMEM_ADDR_SIZE - 1), %l5	
74
	
87
	
75
	/*
88
	/*
76
	 * Setup basic runtime environment.
89
	 * Setup basic runtime environment.
77
	 */
90
	 */
78
 
91
 
Line 81... Line 94...
81
						! never need again
94
						! never need again
82
	wrpr %g0, 0, %otherwin			! make sure the window state is
95
	wrpr %g0, 0, %otherwin			! make sure the window state is
83
						! consistent
96
						! consistent
84
	wrpr %g0, NWINDOWS - 1, %cleanwin	! prevent needless clean_window
97
	wrpr %g0, NWINDOWS - 1, %cleanwin	! prevent needless clean_window
85
						! traps for kernel
98
						! traps for kernel
-
 
99
						
-
 
100
	wrpr %g0, 0, %wstate			! use default spill/fill trap
86
 
101
 
87
	wrpr %g0, 0, %tl			! TL = 0, primary context
102
	wrpr %g0, 0, %tl			! TL = 0, primary context
88
						! register is used
103
						! register is used
89
 
104
 
90
	wrpr %g0, PSTATE_PRIV_BIT, %pstate	! disable interrupts and disable
105
	wrpr %g0, PSTATE_PRIV_BIT, %pstate	! disable interrupts and disable
Line 242... Line 257...
242
	sethi %hi(physmem_base), %l4
257
	sethi %hi(physmem_base), %l4
243
	stx %l6, [%l4 + %lo(physmem_base)]
258
	stx %l6, [%l4 + %lo(physmem_base)]
244
 
259
 
245
	/*
260
	/*
246
	 * Precompute kernel 8K TLB data template.
261
	 * Precompute kernel 8K TLB data template.
247
	 * %l5 contains starting physical address bits [40:13]
262
	 * %l5 contains starting physical address
-
 
263
	 * bits [(PHYSMEM_ADDR_SIZE - 1):13]
248
	 */
264
	 */
249
	sethi %hi(kernel_8k_tlb_data_template), %l4
265
	sethi %hi(kernel_8k_tlb_data_template), %l4
250
	ldx [%l4 + %lo(kernel_8k_tlb_data_template)], %l3
266
	ldx [%l4 + %lo(kernel_8k_tlb_data_template)], %l3
251
	or %l3, %l5, %l3
267
	or %l3, %l5, %l3
252
	stx %l3, [%l4 + %lo(kernel_8k_tlb_data_template)]
268
	stx %l3, [%l4 + %lo(kernel_8k_tlb_data_template)]
Line 280... Line 296...
280
0:
296
0:
281
	ba 0b
297
	ba 0b
282
	nop
298
	nop
283
 
299
 
284
 
300
 
-
 
301
1:
-
 
302
#ifdef CONFIG_SMP
-
 
303
	/*
-
 
304
	 * Determine the width of the MID and save its mask to %g3. The width
-
 
305
	 * is
-
 
306
	 * 	* 5 for US and US-IIIi,
-
 
307
	 * 	* 10 for US3 except US-IIIi.
-
 
308
	 */
-
 
309
#if defined(US)
-
 
310
	mov 0x1f, %g3
-
 
311
#elif defined(US3)
-
 
312
	mov 0x3ff, %g3
-
 
313
	rdpr %ver, %g2
-
 
314
	sllx %g2, 16, %g2
-
 
315
	srlx %g2, 48, %g2
-
 
316
	cmp %g2, IMPL_ULTRASPARCIII_I
-
 
317
	move %xcc, 0x1f, %g3
-
 
318
#endif
-
 
319
 
285
	/*
320
	/*
286
	 * Read MID from the processor.
321
	 * Read MID from the processor.
287
	 */
322
	 */
288
1:
-
 
289
	ldxa [%g0] ASI_UPA_CONFIG, %g1
323
	ldxa [%g0] ASI_ICBUS_CONFIG, %g1
290
	srlx %g1, UPA_CONFIG_MID_SHIFT, %g1
324
	srlx %g1, ICBUS_CONFIG_MID_SHIFT, %g1
291
	and %g1, UPA_CONFIG_MID_MASK, %g1
325
	and %g1, %g3, %g1
292
 
326
 
293
#ifdef CONFIG_SMP
-
 
294
	/*
327
	/*
295
	 * Active loop for APs until the BSP picks them up. A processor cannot
328
	 * Active loop for APs until the BSP picks them up. A processor cannot
296
	 * leave the loop until the global variable 'waking_up_mid' equals its
329
	 * leave the loop until the global variable 'waking_up_mid' equals its
297
	 * MID.
330
	 * MID.
298
	 */
331
	 */