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Rev 3022 Rev 4055
Line 40... Line 40...
40
#include <mm/page.h>
40
#include <mm/page.h>
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#include <mm/slab.h>
41
#include <mm/slab.h>
42
#include <arch/types.h>
42
#include <arch/types.h>
43
#include <debug.h>
43
#include <debug.h>
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#include <print.h>
44
#include <print.h>
45
#include <func.h>
45
#include <string.h>
46
#include <arch/asm.h>
46
#include <arch/asm.h>
-
 
47
#include <sysinfo/sysinfo.h>
47
 
48
 
48
#define PCI_SABRE_REGS_REG  0
49
#define SABRE_INTERNAL_REG  0
-
 
50
#define PSYCHO_INTERNAL_REG 2   
49
 
51
 
50
#define PCI_SABRE_IMAP_BASE 0x200
52
#define OBIO_IMR_BASE   0x200
51
#define PCI_SABRE_ICLR_BASE 0x300
53
#define OBIO_IMR(ino)   (OBIO_IMR_BASE + ((ino) & INO_MASK))
52
 
54
 
53
#define PCI_PSYCHO_REGS_REG 2   
55
#define OBIO_CIR_BASE   0x300
-
 
56
#define OBIO_CIR(ino)   (OBIO_CIR_BASE + ((ino) & INO_MASK))
54
 
57
 
55
#define PCI_PSYCHO_IMAP_BASE    0x200
58
static void obio_enable_interrupt(pci_t *, int);
56
#define PCI_PSYCHO_ICLR_BASE    0x300   
59
static void obio_clear_interrupt(pci_t *, int);
57
 
60
 
58
static pci_t *pci_sabre_init(ofw_tree_node_t *node);
61
static pci_t *pci_sabre_init(ofw_tree_node_t *);
59
static void pci_sabre_enable_interrupt(pci_t *pci, int inr);
-
 
60
static void pci_sabre_clear_interrupt(pci_t *pci, int inr);
-
 
61
 
-
 
62
static pci_t *pci_psycho_init(ofw_tree_node_t *node);
62
static pci_t *pci_psycho_init(ofw_tree_node_t *);
63
static void pci_psycho_enable_interrupt(pci_t *pci, int inr);
-
 
64
static void pci_psycho_clear_interrupt(pci_t *pci, int inr);
-
 
65
 
63
 
66
/** PCI operations for Sabre model. */
64
/** PCI operations for Sabre model. */
67
static pci_operations_t pci_sabre_ops = {
65
static pci_operations_t pci_sabre_ops = {
68
    .enable_interrupt = pci_sabre_enable_interrupt,
66
    .enable_interrupt = obio_enable_interrupt,
69
    .clear_interrupt = pci_sabre_clear_interrupt
67
    .clear_interrupt = obio_clear_interrupt
70
};
68
};
71
/** PCI operations for Psycho model. */
69
/** PCI operations for Psycho model. */
72
static pci_operations_t pci_psycho_ops = {
70
static pci_operations_t pci_psycho_ops = {
73
    .enable_interrupt = pci_psycho_enable_interrupt,
71
    .enable_interrupt = obio_enable_interrupt,
74
    .clear_interrupt = pci_psycho_clear_interrupt
72
    .clear_interrupt = obio_clear_interrupt
75
};
73
};
76
 
74
 
77
/** Initialize PCI controller (model Sabre).
75
/** Initialize PCI controller (model Sabre).
78
 *
76
 *
79
 * @param node OpenFirmware device tree node of the Sabre.
77
 * @param node      OpenFirmware device tree node of the Sabre.
80
 *
78
 *
81
 * @return Address of the initialized PCI structure.
79
 * @return      Address of the initialized PCI structure.
82
 */
80
 */
83
pci_t *pci_sabre_init(ofw_tree_node_t *node)
81
pci_t *pci_sabre_init(ofw_tree_node_t *node)
84
{
82
{
85
    pci_t *pci;
83
    pci_t *pci;
86
    ofw_tree_property_t *prop;
84
    ofw_tree_property_t *prop;
Line 93... Line 91...
93
        return NULL;
91
        return NULL;
94
 
92
 
95
    ofw_upa_reg_t *reg = prop->value;
93
    ofw_upa_reg_t *reg = prop->value;
96
    count_t regs = prop->size / sizeof(ofw_upa_reg_t);
94
    count_t regs = prop->size / sizeof(ofw_upa_reg_t);
97
 
95
 
98
    if (regs < PCI_SABRE_REGS_REG + 1)
96
    if (regs < SABRE_INTERNAL_REG + 1)
99
        return NULL;
97
        return NULL;
100
 
98
 
101
    uintptr_t paddr;
99
    uintptr_t paddr;
102
    if (!ofw_upa_apply_ranges(node->parent, &reg[PCI_SABRE_REGS_REG], &paddr))
100
    if (!ofw_upa_apply_ranges(node->parent, &reg[SABRE_INTERNAL_REG],
-
 
101
        &paddr))
103
        return NULL;
102
        return NULL;
104
 
103
 
105
    pci = (pci_t *) malloc(sizeof(pci_t), FRAME_ATOMIC);
104
    pci = (pci_t *) malloc(sizeof(pci_t), FRAME_ATOMIC);
106
    if (!pci)
105
    if (!pci)
107
        return NULL;
106
        return NULL;
108
 
107
 
109
    pci->model = PCI_SABRE;
108
    pci->model = PCI_SABRE;
110
    pci->op = &pci_sabre_ops;
109
    pci->op = &pci_sabre_ops;
111
    pci->reg = (uint64_t *) hw_map(paddr, reg[PCI_SABRE_REGS_REG].size);
110
    pci->reg = (uint64_t *) hw_map(paddr, reg[SABRE_INTERNAL_REG].size);
-
 
111
 
-
 
112
    /*
-
 
113
     * Set sysinfo data needed by the uspace OBIO driver.
-
 
114
     */
-
 
115
    sysinfo_set_item_val("obio.base.physical", NULL, paddr);
-
 
116
    sysinfo_set_item_val("kbd.cir.obio", NULL, 1);
112
 
117
 
113
    return pci;
118
    return pci;
114
}
119
}
115
 
120
 
116
 
121
 
117
/** Initialize the Psycho PCI controller.
122
/** Initialize the Psycho PCI controller.
118
 *
123
 *
119
 * @param node OpenFirmware device tree node of the Psycho.
124
 * @param node      OpenFirmware device tree node of the Psycho.
120
 *
125
 *
121
 * @return Address of the initialized PCI structure.
126
 * @return      Address of the initialized PCI structure.
122
 */
127
 */
123
pci_t *pci_psycho_init(ofw_tree_node_t *node)
128
pci_t *pci_psycho_init(ofw_tree_node_t *node)
124
{
129
{
125
    pci_t *pci;
130
    pci_t *pci;
126
    ofw_tree_property_t *prop;
131
    ofw_tree_property_t *prop;
Line 133... Line 138...
133
        return NULL;
138
        return NULL;
134
 
139
 
135
    ofw_upa_reg_t *reg = prop->value;
140
    ofw_upa_reg_t *reg = prop->value;
136
    count_t regs = prop->size / sizeof(ofw_upa_reg_t);
141
    count_t regs = prop->size / sizeof(ofw_upa_reg_t);
137
 
142
 
138
    if (regs < PCI_PSYCHO_REGS_REG + 1)
143
    if (regs < PSYCHO_INTERNAL_REG + 1)
139
        return NULL;
144
        return NULL;
140
 
145
 
141
    uintptr_t paddr;
146
    uintptr_t paddr;
142
    if (!ofw_upa_apply_ranges(node->parent, &reg[PCI_PSYCHO_REGS_REG], &paddr))
147
    if (!ofw_upa_apply_ranges(node->parent, &reg[PSYCHO_INTERNAL_REG],
-
 
148
        &paddr))
143
        return NULL;
149
        return NULL;
144
 
150
 
145
    pci = (pci_t *) malloc(sizeof(pci_t), FRAME_ATOMIC);
151
    pci = (pci_t *) malloc(sizeof(pci_t), FRAME_ATOMIC);
146
    if (!pci)
152
    if (!pci)
147
        return NULL;
153
        return NULL;
148
 
154
 
149
    pci->model = PCI_PSYCHO;
155
    pci->model = PCI_PSYCHO;
150
    pci->op = &pci_psycho_ops;
156
    pci->op = &pci_psycho_ops;
151
    pci->reg = (uint64_t *) hw_map(paddr, reg[PCI_PSYCHO_REGS_REG].size);
157
    pci->reg = (uint64_t *) hw_map(paddr, reg[PSYCHO_INTERNAL_REG].size);
152
 
-
 
153
    return pci;
-
 
154
}
-
 
155
 
158
 
156
void pci_sabre_enable_interrupt(pci_t *pci, int inr)
-
 
157
{
159
    /*
158
    pci->reg[PCI_SABRE_IMAP_BASE + (inr & INO_MASK)] |= IMAP_V_MASK;
160
     * Set sysinfo data needed by the uspace OBIO driver.
159
}
161
     */
-
 
162
    sysinfo_set_item_val("obio.base.physical", NULL, paddr);
-
 
163
    sysinfo_set_item_val("kbd.cir.obio", NULL, 1);
160
 
164
 
161
void pci_sabre_clear_interrupt(pci_t *pci, int inr)
165
    return pci;
162
{
-
 
163
    pci->reg[PCI_SABRE_ICLR_BASE + (inr & INO_MASK)] = 0;
-
 
164
}
166
}
165
 
167
 
166
void pci_psycho_enable_interrupt(pci_t *pci, int inr)
168
void obio_enable_interrupt(pci_t *pci, int inr)
167
{
169
{
168
    pci->reg[PCI_PSYCHO_IMAP_BASE + (inr & INO_MASK)] |= IMAP_V_MASK;
170
    pci->reg[OBIO_IMR(inr & INO_MASK)] |= IMAP_V_MASK;
169
}
171
}
170
 
172
 
171
void pci_psycho_clear_interrupt(pci_t *pci, int inr)
173
void obio_clear_interrupt(pci_t *pci, int inr)
172
{
174
{
173
    pci->reg[PCI_PSYCHO_ICLR_BASE + (inr & INO_MASK)] = 0;
175
    pci->reg[OBIO_CIR(inr & INO_MASK)] = 0; /* set IDLE */
174
}
176
}
175
 
177
 
176
/** Initialize PCI controller. */
178
/** Initialize PCI controller. */
177
pci_t *pci_init(ofw_tree_node_t *node)
179
pci_t *pci_init(ofw_tree_node_t *node)
178
{
180
{
Line 213... Line 215...
213
    return NULL;
215
    return NULL;
214
}
216
}
215
 
217
 
216
void pci_enable_interrupt(pci_t *pci, int inr)
218
void pci_enable_interrupt(pci_t *pci, int inr)
217
{
219
{
218
    ASSERT(pci->model);
-
 
219
    ASSERT(pci->op && pci->op->enable_interrupt);
220
    ASSERT(pci->op && pci->op->enable_interrupt);
220
    pci->op->enable_interrupt(pci, inr);
221
    pci->op->enable_interrupt(pci, inr);
221
}
222
}
222
 
223
 
223
void pci_clear_interrupt(pci_t *pci, int inr)
224
void pci_clear_interrupt(void *pcip, int inr)
224
{
225
{
225
    ASSERT(pci->model);
226
    pci_t *pci = (pci_t *)pcip;
-
 
227
 
226
    ASSERT(pci->op && pci->op->clear_interrupt);
228
    ASSERT(pci->op && pci->op->clear_interrupt);
227
    pci->op->clear_interrupt(pci, inr);
229
    pci->op->clear_interrupt(pci, inr);
228
}
230
}
229
 
231
 
230
/** @}
232
/** @}