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#include <arch/memstr.h>
38
#include <arch/memstr.h>
39
#include <arch/regutils.h>
39
#include <arch/regutils.h>
40
#include <interrupt.h>
40
#include <interrupt.h>
41
#include <arch/machine.h>
41
#include <arch/machine.h>
42
#include <arch/mm/page_fault.h>
42
#include <arch/mm/page_fault.h>
-
 
43
#include <arch/barrier.h>
43
#include <print.h>
44
#include <print.h>
44
#include <syscall/syscall.h>
45
#include <syscall/syscall.h>
45
 
46
 
46
/** Offset used in calculation of exception handler's relative address.
47
/** Offset used in calculation of exception handler's relative address.
47
 *
48
 *
Line 60... Line 61...
60
 
61
 
61
/** Switches to kernel stack and saves all registers there.
62
/** Switches to kernel stack and saves all registers there.
62
 *
63
 *
63
 * Temporary exception stack is used to save a few registers
64
 * Temporary exception stack is used to save a few registers
64
 * before stack switch takes place.
65
 * before stack switch takes place.
-
 
66
 *
65
 */
67
 */
66
inline static void setup_stack_and_save_regs()
68
inline static void setup_stack_and_save_regs()
67
{
69
{
68
    asm volatile(
70
    asm volatile (
69
        "ldr r13, =exc_stack        \n"
71
        "ldr r13, =exc_stack\n"
70
        "stmfd r13!, {r0}       \n"
72
        "stmfd r13!, {r0}\n"
71
        "mrs r0, spsr           \n"
73
        "mrs r0, spsr\n"
72
        "and r0, r0, #0x1f      \n"
74
        "and r0, r0, #0x1f\n"
73
        "cmp r0, #0x10          \n"
75
        "cmp r0, #0x10\n"
74
        "bne 1f             \n"
76
        "bne 1f\n"
75
 
77
       
76
        /* prev mode was usermode */
78
        /* prev mode was usermode */
77
        "ldmfd r13!, {r0}       \n"
79
        "ldmfd r13!, {r0}\n"
78
        "ldr r13, =supervisor_sp    \n"
80
        "ldr r13, =supervisor_sp\n"
79
        "ldr r13, [r13]         \n"
81
        "ldr r13, [r13]\n"
80
        "stmfd r13!, {lr}       \n"
82
        "stmfd r13!, {lr}\n"
81
        "stmfd r13!, {r0-r12}       \n"
83
        "stmfd r13!, {r0-r12}\n"
82
        "stmfd r13!, {r13, lr}^     \n"
84
        "stmfd r13!, {r13, lr}^\n"
83
        "mrs r0, spsr           \n"
85
        "mrs r0, spsr\n"
84
        "stmfd r13!, {r0}       \n"
86
        "stmfd r13!, {r0}\n"
85
        "b 2f               \n"
87
        "b 2f\n"
86
 
88
       
87
        /* mode was not usermode */
89
        /* mode was not usermode */
88
    "1:\n"
90
        "1:\n"
89
        "stmfd r13!, {r1, r2, r3}   \n"
91
            "stmfd r13!, {r1, r2, r3}\n"
90
        "mrs r1, cpsr           \n"
92
            "mrs r1, cpsr\n"
91
        "mov r2, lr         \n"
93
            "mov r2, lr\n"
92
        "bic r1, r1, #0x1f      \n"
94
            "bic r1, r1, #0x1f\n"
93
        "orr r1, r1, r0         \n"
95
            "orr r1, r1, r0\n"
94
        "mrs r0, cpsr           \n"
96
            "mrs r0, cpsr\n"
95
        "msr cpsr_c, r1         \n"
97
            "msr cpsr_c, r1\n"
96
 
98
           
97
        "mov r3, r13            \n"
99
            "mov r3, r13\n"
98
        "stmfd r13!, {r2}       \n"
100
            "stmfd r13!, {r2}\n"
99
        "mov r2, lr         \n"
101
            "mov r2, lr\n"
100
        "stmfd r13!, {r4-r12}       \n"
102
            "stmfd r13!, {r4-r12}\n"
101
        "mov r1, r13            \n"
103
            "mov r1, r13\n"
-
 
104
           
102
        /* the following two lines are for debugging */
105
            /* the following two lines are for debugging */
103
        "mov sp, #0         \n"
106
            "mov sp, #0\n"
104
        "mov lr, #0         \n"
107
            "mov lr, #0\n"
105
        "msr cpsr_c, r0         \n"
108
            "msr cpsr_c, r0\n"
106
 
109
           
107
        "ldmfd r13!, {r4, r5, r6, r7}   \n"
110
            "ldmfd r13!, {r4, r5, r6, r7}\n"
108
        "stmfd r1!, {r4, r5, r6}    \n"
111
            "stmfd r1!, {r4, r5, r6}\n"
109
        "stmfd r1!, {r7}        \n"
112
            "stmfd r1!, {r7}\n"
110
        "stmfd r1!, {r2}        \n"
113
            "stmfd r1!, {r2}\n"
111
        "stmfd r1!, {r3}        \n"
114
            "stmfd r1!, {r3}\n"
112
        "mrs r0, spsr           \n"
115
            "mrs r0, spsr\n"
113
        "stmfd r1!, {r0}        \n"
116
            "stmfd r1!, {r0}\n"
114
        "mov r13, r1            \n"
117
            "mov r13, r1\n"
-
 
118
           
115
    "2:\n"
119
        "2:\n"
116
    );
120
    );
117
}
121
}
118
 
122
 
119
/** Returns from exception mode.
123
/** Returns from exception mode.
120
 *
124
 *
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186
        "ldmfd sp!, {r0-r3}     \n"
190
        "ldmfd sp!, {r0-r3}     \n"
187
    );
191
    );
188
}
192
}
189
 
193
 
190
/** Calls exception dispatch routine. */
194
/** Calls exception dispatch routine. */
191
#define CALL_EXC_DISPATCH(exception)        \
195
#define CALL_EXC_DISPATCH(exception) \
-
 
196
    asm volatile ( \
192
    asm("mov r0, %0" : : "i" (exception));  \
197
        "mov r0, %[exc]\n" \
193
    asm("mov r1, r13");         \
198
        "mov r1, r13\n" \
194
    asm("bl exc_dispatch");     
199
        "bl exc_dispatch\n" \
-
 
200
        :: [exc] "i" (exception) \
-
 
201
    );\
195
 
202
 
196
/** General exception handler.
203
/** General exception handler.
197
 *
204
 *
198
 *  Stores registers, dispatches the exception,
205
 *  Stores registers, dispatches the exception,
199
 *  and finally restores registers and returns from exception processing.
206
 *  and finally restores registers and returns from exception processing.
200
 *
207
 *
201
 *  @param exception Exception number.
208
 *  @param exception Exception number.
202
 */
209
 */
203
#define PROCESS_EXCEPTION(exception)        \
210
#define PROCESS_EXCEPTION(exception) \
204
    setup_stack_and_save_regs();        \
211
    setup_stack_and_save_regs(); \
205
    CALL_EXC_DISPATCH(exception)        \
212
    CALL_EXC_DISPATCH(exception) \
206
    load_regs();
213
    load_regs();
207
 
214
 
208
/** Updates specified exception vector to jump to given handler.
215
/** Updates specified exception vector to jump to given handler.
209
 *
216
 *
210
 *  Addresses of handlers are stored in memory following exception vectors.
217
 *  Addresses of handlers are stored in memory following exception vectors.
211
 */
218
 */
212
static void install_handler (unsigned handler_addr, unsigned* vector)
219
static void install_handler(unsigned handler_addr, unsigned *vector)
213
{
220
{
214
    /* relative address (related to exc. vector) of the word
221
    /* relative address (related to exc. vector) of the word
215
     * where handler's address is stored
222
     * where handler's address is stored
216
    */
223
    */
217
    volatile uint32_t handler_address_ptr = EXC_VECTORS_SIZE -
224
    volatile uint32_t handler_address_ptr = EXC_VECTORS_SIZE -
218
        PREFETCH_OFFSET;
225
        PREFETCH_OFFSET;
219
   
226
   
220
    /* make it LDR instruction and store at exception vector */
227
    /* make it LDR instruction and store at exception vector */
221
    *vector = handler_address_ptr | LDR_OPCODE;
228
    *vector = handler_address_ptr | LDR_OPCODE;
-
 
229
    smc_coherence(*vector);
222
   
230
   
223
    /* store handler's address */
231
    /* store handler's address */
224
    *(vector + EXC_VECTORS) = handler_addr;
232
    *(vector + EXC_VECTORS) = handler_addr;
225
 
233
 
226
}
234
}
227
 
235
 
228
/** Low-level Reset Exception handler. */
236
/** Low-level Reset Exception handler. */
229
static void reset_exception_entry()
237
static void reset_exception_entry(void)
230
{
238
{
231
    PROCESS_EXCEPTION(EXC_RESET);
239
    PROCESS_EXCEPTION(EXC_RESET);
232
}
240
}
233
 
241
 
234
/** Low-level Software Interrupt Exception handler. */
242
/** Low-level Software Interrupt Exception handler. */
235
static void swi_exception_entry()
243
static void swi_exception_entry(void)
236
{
244
{
237
    PROCESS_EXCEPTION(EXC_SWI);
245
    PROCESS_EXCEPTION(EXC_SWI);
238
}
246
}
239
 
247
 
240
/** Low-level Undefined Instruction Exception handler. */
248
/** Low-level Undefined Instruction Exception handler. */
241
static void undef_instr_exception_entry()
249
static void undef_instr_exception_entry(void)
242
{
250
{
243
    PROCESS_EXCEPTION(EXC_UNDEF_INSTR);
251
    PROCESS_EXCEPTION(EXC_UNDEF_INSTR);
244
}
252
}
245
 
253
 
246
/** Low-level Fast Interrupt Exception handler. */
254
/** Low-level Fast Interrupt Exception handler. */
247
static void fiq_exception_entry()
255
static void fiq_exception_entry(void)
248
{
256
{
249
    PROCESS_EXCEPTION(EXC_FIQ);
257
    PROCESS_EXCEPTION(EXC_FIQ);
250
}
258
}
251
 
259
 
252
/** Low-level Prefetch Abort Exception handler. */
260
/** Low-level Prefetch Abort Exception handler. */
253
static void prefetch_abort_exception_entry()
261
static void prefetch_abort_exception_entry(void)
254
{
262
{
255
    asm("sub lr, lr, #4");
263
    asm("sub lr, lr, #4");
256
    PROCESS_EXCEPTION(EXC_PREFETCH_ABORT);
264
    PROCESS_EXCEPTION(EXC_PREFETCH_ABORT);
257
}
265
}
258
 
266
 
259
/** Low-level Data Abort Exception handler. */
267
/** Low-level Data Abort Exception handler. */
260
static void data_abort_exception_entry()
268
static void data_abort_exception_entry(void)
261
{
269
{
262
    asm("sub lr, lr, #8");
270
    asm("sub lr, lr, #8");
263
    PROCESS_EXCEPTION(EXC_DATA_ABORT);
271
    PROCESS_EXCEPTION(EXC_DATA_ABORT);
264
}
272
}
265
 
273
 
Line 267... Line 275...
267
 *
275
 *
268
 * CPU is switched to Undefined mode before further interrupt processing
276
 * CPU is switched to Undefined mode before further interrupt processing
269
 * because of possible occurence of nested interrupt exception, which
277
 * because of possible occurence of nested interrupt exception, which
270
 * would overwrite (and thus spoil) stack pointer.
278
 * would overwrite (and thus spoil) stack pointer.
271
 */
279
 */
272
static void irq_exception_entry()
280
static void irq_exception_entry(void)
273
{
281
{
274
    asm("sub lr, lr, #4");
282
    asm("sub lr, lr, #4");
275
    setup_stack_and_save_regs();
283
    setup_stack_and_save_regs();
276
   
284
   
277
    switch_to_irq_servicing_mode();
285
    switch_to_irq_servicing_mode();
Line 329... Line 337...
329
/** Activates use of high exception vectors addresses. */
337
/** Activates use of high exception vectors addresses. */
330
static void high_vectors(void)
338
static void high_vectors(void)
331
{
339
{
332
    uint32_t control_reg;
340
    uint32_t control_reg;
333
   
341
   
-
 
342
    asm volatile (
-
 
343
        "mrc p15, 0, %[control_reg], c1, c1"
334
    asm volatile("mrc p15, 0, %0, c1, c1" : "=r" (control_reg));
344
        : [control_reg] "=r" (control_reg)
-
 
345
    );
335
   
346
   
336
    /* switch on the high vectors bit */
347
    /* switch on the high vectors bit */
337
    control_reg |= CP15_R1_HIGH_VECTORS_BIT;
348
    control_reg |= CP15_R1_HIGH_VECTORS_BIT;
338
   
349
   
-
 
350
    asm volatile (
-
 
351
        "mcr p15, 0, %[control_reg], c1, c1"
339
    asm volatile("mcr p15, 0, %0, c1, c1" : : "r" (control_reg));
352
        :: [control_reg] "r" (control_reg)
-
 
353
    );
340
}
354
}
341
#endif
355
#endif
342
 
356
 
343
/** Initializes exception handling.
357
/** Initializes exception handling.
344
 *
358
 *
345
 * Installs low-level exception handlers and then registers
359
 * Installs low-level exception handlers and then registers
346
 * exceptions and their handlers to kernel exception dispatcher.
360
 * exceptions and their handlers to kernel exception dispatcher.
347
 */
361
 */
348
void exception_init(void)
362
void exception_init(void)
349
{
363
{