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1 | /* |
1 | /* |
2 | * Copyright (c) 2006 Jakub Jermar |
2 | * Copyright (c) 2007 Pavel Jancik, Michal Kebrt |
3 | * All rights reserved. |
3 | * All rights reserved. |
4 | * |
4 | * |
5 | * Redistribution and use in source and binary forms, with or without |
5 | * Redistribution and use in source and binary forms, with or without |
6 | * modification, are permitted provided that the following conditions |
6 | * modification, are permitted provided that the following conditions |
7 | * are met: |
7 | * are met: |
Line 24... | Line 24... | ||
24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
27 | */ |
27 | */ |
28 | 28 | ||
29 | /** @addtogroup libcia64 |
29 | /** @addtogroup libcarm32 |
30 | * @{ |
30 | * @{ |
31 | */ |
31 | */ |
32 | /** @file |
32 | /** @file |
- | 33 | * @brief Uspace threads and TLS. |
|
33 | */ |
34 | */ |
34 | 35 | ||
35 | #ifndef LIBC_arm32_THREAD_H_ |
36 | #ifndef LIBC_arm32_THREAD_H_ |
36 | #define LIBC_arm32_THREAD_H_ |
37 | #define LIBC_arm32_THREAD_H_ |
37 | 38 | ||
38 | #include <unistd.h> |
39 | #include <unistd.h> |
39 | 40 | ||
- | 41 | /** Stack initial size. */ |
|
40 | #define THREAD_INITIAL_STACK_PAGES_NO 1 |
42 | #define THREAD_INITIAL_STACK_PAGES_NO 1 |
41 | 43 | ||
- | 44 | /** Offsets for accessing __thread variables are shifted 8 bytes higher. */ |
|
42 | #define ARM_TP_OFFSET (-8) |
45 | #define ARM_TP_OFFSET (-8) |
43 | 46 | ||
- | 47 | /** TCB (Thread Control Block) struct. |
|
- | 48 | * |
|
- | 49 | * TLS starts just after this struct. |
|
- | 50 | */ |
|
44 | typedef struct { |
51 | typedef struct { |
- | 52 | /** psthread data. */ |
|
45 | void *pst_data; |
53 | void *pst_data; |
46 | } tcb_t; |
54 | } tcb_t; |
47 | 55 | ||
- | 56 | ||
- | 57 | /** Sets TLS address to the r9 register. |
|
- | 58 | * |
|
- | 59 | * @param tcb TCB (TLS starts behind) |
|
- | 60 | */ |
|
48 | static inline void __tcb_set(tcb_t *tcb) |
61 | static inline void __tcb_set(tcb_t *tcb) |
49 | { |
62 | { |
50 | void *tls = (void *)tcb; |
63 | void *tls = (void *)tcb; |
51 | tls += sizeof(tcb_t) + ARM_TP_OFFSET; |
64 | tls += sizeof(tcb_t) + ARM_TP_OFFSET; |
52 | asm volatile ( |
65 | asm volatile ( |
Line 54... | Line 67... | ||
54 | : |
67 | : |
55 | : "r"(tls) |
68 | : "r"(tls) |
56 | ); |
69 | ); |
57 | } |
70 | } |
58 | 71 | ||
- | 72 | ||
- | 73 | /** Returns TCB address. |
|
- | 74 | * |
|
- | 75 | * @return TCB address (starts before TLS which address is stored in r9 register). |
|
- | 76 | */ |
|
59 | static inline tcb_t *__tcb_get(void) |
77 | static inline tcb_t *__tcb_get(void) |
60 | { |
78 | { |
61 | void *ret; |
79 | void *ret; |
62 | asm volatile ( |
80 | asm volatile ( |
63 | "mov %0, r9" |
81 | "mov %0, r9" |
64 | : "=r"(ret) |
82 | : "=r"(ret) |
65 | ); |
83 | ); |
66 | return (tcb_t *)(ret - ARM_TP_OFFSET - sizeof(tcb_t)); |
84 | return (tcb_t *)(ret - ARM_TP_OFFSET - sizeof(tcb_t)); |
67 | } |
85 | } |
68 | 86 | ||
- | 87 | ||
- | 88 | /** Returns TLS address stored. |
|
- | 89 | * |
|
- | 90 | * Implemented in assembly. |
|
- | 91 | * |
|
- | 92 | * @return TLS address stored in r9 register |
|
- | 93 | */ |
|
- | 94 | extern uintptr_t __aeabi_read_tp(void); |
|
- | 95 | ||
69 | #endif |
96 | #endif |
70 | 97 | ||
71 | /** @} |
98 | /** @} |
72 | */ |
99 | */ |