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| 42 | 42 | ||
| 43 | 43 | ||
| 44 | /** Returns value stored in fault status register. |
44 | /** Returns value stored in fault status register. |
| 45 | * FSR contain reason of page fault |
45 | * FSR contain reason of page fault |
| 46 | * |
46 | * |
| 47 | * \return Value stored in CP15 fault status register (FSR). |
47 | * @return Value stored in CP15 fault status register (FSR). |
| 48 | */ |
48 | */ |
| 49 | static inline fault_status_t read_fault_status_register(void) |
49 | static inline fault_status_t read_fault_status_register(void) |
| 50 | { |
50 | { |
| 51 | fault_status_union_t fsu; |
51 | fault_status_union_t fsu; |
| 52 | 52 | ||
| Line 59... | Line 59... | ||
| 59 | } |
59 | } |
| 60 | 60 | ||
| 61 | 61 | ||
| 62 | /** Returns FAR (fault address register) content. |
62 | /** Returns FAR (fault address register) content. |
| 63 | * |
63 | * |
| 64 | * \return FAR (fault address register) content (address that caused a page fault) |
64 | * @return FAR (fault address register) content (address that caused a page fault) |
| 65 | */ |
65 | */ |
| 66 | static inline uintptr_t read_fault_address_register(void) |
66 | static inline uintptr_t read_fault_address_register(void) |
| 67 | { |
67 | { |
| 68 | uintptr_t ret; |
68 | uintptr_t ret; |
| 69 | 69 | ||
| Line 76... | Line 76... | ||
| 76 | } |
76 | } |
| 77 | 77 | ||
| 78 | 78 | ||
| 79 | /** Decides whether the instructions is load/store or not. |
79 | /** Decides whether the instructions is load/store or not. |
| 80 | * |
80 | * |
| 81 | * \param instr Instruction |
81 | * @param instr Instruction |
| 82 | * |
82 | * |
| 83 | * \return true when instruction is load/store, false otherwise |
83 | * @return true when instruction is load/store, false otherwise |
| 84 | */ |
84 | */ |
| 85 | static inline bool is_load_store_instruction(instruction_t instr) |
85 | static inline bool is_load_store_instruction(instruction_t instr) |
| 86 | { |
86 | { |
| 87 | // load store immediate offset |
87 | // load store immediate offset |
| 88 | if (instr.type == 0x2) { |
88 | if (instr.type == 0x2) { |
| Line 108... | Line 108... | ||
| 108 | } |
108 | } |
| 109 | 109 | ||
| 110 | 110 | ||
| 111 | /** Decides whether the instructions is swap or not. |
111 | /** Decides whether the instructions is swap or not. |
| 112 | * |
112 | * |
| 113 | * \param instr Instruction |
113 | * @param instr Instruction |
| 114 | * |
114 | * |
| 115 | * \return true when instruction is swap, false otherwise |
115 | * @return true when instruction is swap, false otherwise |
| 116 | */ |
116 | */ |
| 117 | static inline bool is_swap_instruction(instruction_t instr) |
117 | static inline bool is_swap_instruction(instruction_t instr) |
| 118 | { |
118 | { |
| 119 | // swap, swapb instruction |
119 | // swap, swapb instruction |
| 120 | if (instr.type == 0x0 && |
120 | if (instr.type == 0x0 && |
| Line 127... | Line 127... | ||
| 127 | } |
127 | } |
| 128 | 128 | ||
| 129 | 129 | ||
| 130 | /** Decides whether read or write into memory is requested. |
130 | /** Decides whether read or write into memory is requested. |
| 131 | * |
131 | * |
| 132 | * \param instr_addr Address of instruction which tries to access memory |
132 | * @param instr_addr Address of instruction which tries to access memory |
| 133 | * \param badvaddr Virtual address the instruction tries to access |
133 | * @param badvaddr Virtual address the instruction tries to access |
| 134 | * |
134 | * |
| 135 | * \return Type of access into memmory |
135 | * @return Type of access into memmory |
| 136 | * \note Returns #PF_ACCESS_EXEC if no memory access is requested |
136 | * Note: Returns #PF_ACCESS_EXEC if no memory access is requested |
| 137 | */ |
137 | */ |
| 138 | static pf_access_t get_memory_access_type(uint32_t instr_addr, uintptr_t badvaddr) |
138 | static pf_access_t get_memory_access_type(uint32_t instr_addr, uintptr_t badvaddr) |
| 139 | { |
139 | { |
| 140 | instruction_union_t instr_union; |
140 | instruction_union_t instr_union; |
| 141 | instr_union.pc = instr_addr; |
141 | instr_union.pc = instr_addr; |
| Line 193... | Line 193... | ||
| 193 | return PF_ACCESS_EXEC; |
193 | return PF_ACCESS_EXEC; |
| 194 | } |
194 | } |
| 195 | 195 | ||
| 196 | /** Handles "data abort" exception (load or store at invalid address). |
196 | /** Handles "data abort" exception (load or store at invalid address). |
| 197 | * |
197 | * |
| 198 | * \param exc_no exception number |
198 | * @param exc_no exception number |
| 199 | * \param istate CPU state when exception occured |
199 | * @param istate CPU state when exception occured |
| 200 | */ |
200 | */ |
| 201 | void data_abort(int exc_no, istate_t *istate) |
201 | void data_abort(int exc_no, istate_t *istate) |
| 202 | { |
202 | { |
| 203 | fault_status_t fsr = read_fault_status_register(); |
203 | fault_status_t fsr = read_fault_status_register(); |
| 204 | uintptr_t badvaddr = read_fault_address_register(); |
204 | uintptr_t badvaddr = read_fault_address_register(); |
| Line 217... | Line 217... | ||
| 217 | } |
217 | } |
| 218 | } |
218 | } |
| 219 | 219 | ||
| 220 | /** Handles "prefetch abort" exception (instruction couldn't be executed). |
220 | /** Handles "prefetch abort" exception (instruction couldn't be executed). |
| 221 | * |
221 | * |
| 222 | * \param exc_no exception number |
222 | * @param exc_no exception number |
| 223 | * \param istate CPU state when exception occured |
223 | * @param istate CPU state when exception occured |
| 224 | */ |
224 | */ |
| 225 | void prefetch_abort(int exc_no, istate_t *istate) |
225 | void prefetch_abort(int exc_no, istate_t *istate) |
| 226 | { |
226 | { |
| 227 | int ret = as_page_fault(istate->pc, PF_ACCESS_EXEC, istate); |
227 | int ret = as_page_fault(istate->pc, PF_ACCESS_EXEC, istate); |
| 228 | 228 | ||