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- | 1 | /* |
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- | 2 | * Copyright (c) 2007 Pavel Jancik, Michal Kebrt |
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- | 3 | * All rights reserved. |
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- | 4 | * |
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- | 5 | * Redistribution and use in source and binary forms, with or without |
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- | 6 | * modification, are permitted provided that the following conditions |
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- | 7 | * are met: |
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- | 8 | * |
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- | 9 | * - Redistributions of source code must retain the above copyright |
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- | 10 | * notice, this list of conditions and the following disclaimer. |
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- | 11 | * - Redistributions in binary form must reproduce the above copyright |
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- | 12 | * notice, this list of conditions and the following disclaimer in the |
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- | 13 | * documentation and/or other materials provided with the distribution. |
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- | 14 | * - The name of the author may not be used to endorse or promote products |
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- | 15 | * derived from this software without specific prior written permission. |
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- | 16 | * |
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- | 17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
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- | 18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
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- | 19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
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- | 20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
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- | 21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
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- | 22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
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- | 23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
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- | 24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
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- | 25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
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- | 26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
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- | 27 | */ |
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- | 28 | ||
- | 29 | /** @addtogroup arm32mm |
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- | 30 | * @{ |
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- | 31 | */ |
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- | 32 | /** @file |
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- | 33 | * @brief Page fault related functions. |
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- | 34 | */ |
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- | 35 | #include <panic.h> |
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- | 36 | #include <arch/exception.h> |
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- | 37 | #include <arch/debug/print.h> |
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- | 38 | #include <arch/mm/page_fault.h> |
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- | 39 | #include <mm/as.h> |
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- | 40 | #include <genarch/mm/page_pt.h> |
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- | 41 | #include <arch.h> |
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- | 42 | #include <interrupt.h> |
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- | 43 | #include <print.h> |
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- | 44 | ||
- | 45 | /** Returns value stored in fault status register. |
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- | 46 | * |
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- | 47 | * @return Value stored in CP15 fault status register (FSR). |
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- | 48 | */ |
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- | 49 | static inline fault_status_t read_fault_status_register(void) |
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- | 50 | { |
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- | 51 | fault_status_union_t fsu; |
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- | 52 | ||
- | 53 | /* fault status is stored in CP15 register 5 */ |
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- | 54 | asm volatile ( |
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- | 55 | "mrc p15, 0, %0, c5, c0, 0" |
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- | 56 | : "=r"(fsu.dummy) |
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- | 57 | ); |
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- | 58 | return fsu.fs; |
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- | 59 | } |
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- | 60 | ||
- | 61 | /** Returns FAR (fault address register) content. |
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- | 62 | * |
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- | 63 | * @return FAR (fault address register) content (address that caused a page |
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- | 64 | * fault) |
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- | 65 | */ |
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- | 66 | static inline uintptr_t read_fault_address_register(void) |
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- | 67 | { |
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- | 68 | uintptr_t ret; |
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- | 69 | ||
- | 70 | /* fault adress is stored in CP15 register 6 */ |
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- | 71 | asm volatile ( |
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- | 72 | "mrc p15, 0, %0, c6, c0, 0" |
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- | 73 | : "=r"(ret) |
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- | 74 | ); |
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- | 75 | return ret; |
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- | 76 | } |
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- | 77 | ||
- | 78 | /** Decides whether the instruction is load/store or not. |
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- | 79 | * |
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- | 80 | * @param instr Instruction |
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- | 81 | * |
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- | 82 | * @return true when instruction is load/store, false otherwise |
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- | 83 | */ |
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- | 84 | static inline bool is_load_store_instruction(instruction_t instr) |
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- | 85 | { |
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- | 86 | /* load store immediate offset */ |
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- | 87 | if (instr.type == 0x2) { |
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- | 88 | return true; |
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- | 89 | } |
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- | 90 | ||
- | 91 | /* load store register offset */ |
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- | 92 | if (instr.type == 0x3 && instr.bit4 == 0) { |
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- | 93 | return true; |
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- | 94 | } |
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- | 95 | ||
- | 96 | /* load store multiple */ |
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- | 97 | if (instr.type == 0x4) { |
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- | 98 | return true; |
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- | 99 | } |
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- | 100 | ||
- | 101 | /* oprocessor load/store */ |
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- | 102 | if (instr.type == 0x6) { |
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- | 103 | return true; |
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- | 104 | } |
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- | 105 | ||
- | 106 | return false; |
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- | 107 | } |
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- | 108 | ||
- | 109 | /** Decides whether the instruction is swap or not. |
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- | 110 | * |
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- | 111 | * @param instr Instruction |
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- | 112 | * |
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- | 113 | * @return true when instruction is swap, false otherwise |
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- | 114 | */ |
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- | 115 | static inline bool is_swap_instruction(instruction_t instr) |
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- | 116 | { |
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- | 117 | /* swap, swapb instruction */ |
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- | 118 | if (instr.type == 0x0 && |
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- | 119 | (instr.opcode == 0x8 || instr.opcode == 0xa) && |
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- | 120 | instr.access == 0x0 && instr.bits567 == 0x4 && instr.bit4 == 1) { |
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- | 121 | return true; |
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- | 122 | } |
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- | 123 | ||
- | 124 | return false; |
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- | 125 | } |
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- | 126 | ||
- | 127 | /** Decides whether read or write into memory is requested. |
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- | 128 | * |
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- | 129 | * @param instr_addr Address of instruction which tries to access memory. |
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- | 130 | * @param badvaddr Virtual address the instruction tries to access. |
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- | 131 | * |
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- | 132 | * @return Type of access into memory, PF_ACCESS_EXEC if no memory access is |
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- | 133 | * requested. |
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- | 134 | */ |
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- | 135 | static pf_access_t get_memory_access_type(uint32_t instr_addr, |
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- | 136 | uintptr_t badvaddr) |
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- | 137 | { |
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- | 138 | instruction_union_t instr_union; |
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- | 139 | instr_union.pc = instr_addr; |
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- | 140 | ||
- | 141 | instruction_t instr = *(instr_union.instr); |
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- | 142 | ||
- | 143 | /* undefined instructions */ |
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- | 144 | if (instr.condition == 0xf) { |
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- | 145 | panic("page_fault - instruction doesn't access memory " |
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- | 146 | "(instr_code: %x, badvaddr:%x)", instr, badvaddr); |
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- | 147 | return PF_ACCESS_EXEC; |
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- | 148 | } |
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- | 149 | ||
- | 150 | /* load store instructions */ |
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- | 151 | if (is_load_store_instruction(instr)) { |
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- | 152 | if (instr.access == 1) { |
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- | 153 | return PF_ACCESS_READ; |
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- | 154 | } else { |
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- | 155 | return PF_ACCESS_WRITE; |
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- | 156 | } |
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- | 157 | } |
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- | 158 | ||
- | 159 | /* swap, swpb instruction */ |
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- | 160 | if (is_swap_instruction(instr)) { |
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- | 161 | return PF_ACCESS_WRITE; |
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- | 162 | } |
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- | 163 | ||
- | 164 | panic("page_fault - instruction doesn't access memory " |
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- | 165 | "(instr_code: %x, badvaddr:%x)", instr, badvaddr); |
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- | 166 | ||
- | 167 | return PF_ACCESS_EXEC; |
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- | 168 | } |
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- | 169 | ||
- | 170 | /** Handles "data abort" exception (load or store at invalid address). |
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- | 171 | * |
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- | 172 | * @param exc_no Exception number. |
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- | 173 | * @param istate CPU state when exception occured. |
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- | 174 | */ |
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- | 175 | void data_abort(int exc_no, istate_t *istate) |
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- | 176 | { |
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- | 177 | fault_status_t fsr __attribute__ ((unused)) = |
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- | 178 | read_fault_status_register(); |
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- | 179 | uintptr_t badvaddr = read_fault_address_register(); |
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- | 180 | ||
- | 181 | pf_access_t access = get_memory_access_type(istate->pc, badvaddr); |
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- | 182 | ||
- | 183 | int ret = as_page_fault(badvaddr, access, istate); |
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- | 184 | ||
- | 185 | if (ret == AS_PF_FAULT) { |
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- | 186 | print_istate(istate); |
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- | 187 | dprintf("page fault - pc: %x, va: %x, status: %x(%x), " |
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- | 188 | "access:%d\n", istate->pc, badvaddr, fsr.status, fsr, |
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- | 189 | access); |
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- | 190 | ||
- | 191 | fault_if_from_uspace(istate, "Page fault: %#x", badvaddr); |
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- | 192 | panic("page fault\n"); |
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- | 193 | } |
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- | 194 | } |
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- | 195 | ||
- | 196 | /** Handles "prefetch abort" exception (instruction couldn't be executed). |
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- | 197 | * |
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- | 198 | * @param exc_no Exception number. |
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- | 199 | * @param istate CPU state when exception occured. |
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- | 200 | */ |
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- | 201 | void prefetch_abort(int exc_no, istate_t *istate) |
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- | 202 | { |
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- | 203 | int ret = as_page_fault(istate->pc, PF_ACCESS_EXEC, istate); |
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- | 204 | ||
- | 205 | if (ret == AS_PF_FAULT) { |
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- | 206 | dprintf("prefetch_abort\n"); |
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- | 207 | print_istate(istate); |
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- | 208 | panic("page fault - prefetch_abort at address: %x\n", |
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- | 209 | istate->pc); |
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- | 210 | } |
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- | 211 | } |
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- | 212 | ||
- | 213 | /** @} |
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- | 214 | */ |