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 */
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 */
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#include <arch/mm/page.h>
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#include <arch/mm/page.h>
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#include <genarch/mm/page_pt.h>
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#include <genarch/mm/page_pt.h>
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#include <mm/page.h>
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#include <mm/page.h>
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#include <align.h>
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#include <config.h>
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#include "../aux_print/printf.h"
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void page_arch_init(void)
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void page_arch_init(void)
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{
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{
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    aux_printf("page_arch_init\n");
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    uintptr_t cur;
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    int flags;
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    page_mapping_operations = &pt_mapping_operations;
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    page_mapping_operations = &pt_mapping_operations;
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    flags = PAGE_CACHEABLE;
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    const unsigned maxmem = ALIGN_DOWN(config.memory_size, FRAME_SIZE);
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    for (cur = 0; cur < maxmem; cur += FRAME_SIZE) {
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        page_mapping_insert(AS_KERNEL, PA2KA(cur), cur, flags);
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    }    
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    //TODO set page fault routines
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    // no problem no ... kernel doesn't do page faults
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    asm volatile (
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    "ldr r0, =0x55555555       \n"
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    "mrc p15, 0, r0, c3, c0, 0 \n" //set domain acces rights to client <==> take rights from page tables
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    "mcr p15, 0, r0, c1, c0, 0 \n" // get current setting of system ... register 1 isn't only for memmory management
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    "ldr r1, =0xFFFFFE8D       \n" // mask to disable aligment checks, System, Rom bit disable
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    "and r0, r0, r1            \n"
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    "ldr r1, =0x00000001       \n" // mask to enable paging
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    "orr r0, r0, r1            \n"
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    "mrc p15, 0, r0, c1, c0, 0 \n" // store setting
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    :
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    :
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    : "r0", "r1"
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    );
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}
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}
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/** Map device into kernel space. */
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/** Map device into kernel space. */
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uintptr_t hw_map(uintptr_t physaddr, size_t size)
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uintptr_t hw_map(uintptr_t physaddr, size_t size)
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{
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{
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    return NULL;
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    return NULL;
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}
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}
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/** @}
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/** @}
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 */
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 */
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