Rev 4612 | Go to most recent revision | Show entire file | Ignore whitespace | Details | Blame | Last modification | View Log | RSS feed
| Rev 4612 | Rev 4615 | ||
|---|---|---|---|
| Line 273... | Line 273... | ||
| 273 | * |
273 | * |
| 274 | * @param devno device number. |
274 | * @param devno device number. |
| 275 | */ |
275 | */ |
| 276 | void qemu_icp_console_init(devno_t devno) |
276 | void qemu_icp_console_init(devno_t devno) |
| 277 | { |
277 | { |
| - | 278 | qemu_icp_irqc_mask(QEMU_ICP_KBD_IRQ); |
|
| 278 | chardev_initialize("qemu_icp_console", &console, &qemu_icp_ops); |
279 | chardev_initialize("qemu_icp_console", &console, &qemu_icp_ops); |
| 279 | stdin = &console; |
280 | stdin = &console; |
| 280 | stdout = &console; |
281 | stdout = &console; |
| 281 | 282 | ||
| 282 | irq_initialize(&qemu_icp_console_irq); |
283 | irq_initialize(&qemu_icp_console_irq); |
| Line 298... | Line 299... | ||
| 298 | * |
299 | * |
| 299 | * @param frequency Interrupts frequency (0 disables RTC). |
300 | * @param frequency Interrupts frequency (0 disables RTC). |
| 300 | */ |
301 | */ |
| 301 | static void qemu_icp_timer_start(uint32_t frequency) |
302 | static void qemu_icp_timer_start(uint32_t frequency) |
| 302 | { |
303 | { |
| - | 304 | qemu_icp_irqc_mask(QEMU_ICP_TIMER_IRQ); |
|
| 303 | *((uint32_t*) qemu_icp_hw_map.rtc1_load) = frequency; |
305 | *((uint32_t*) qemu_icp_hw_map.rtc1_load) = frequency; |
| 304 | *((uint32_t*) qemu_icp_hw_map.rtc1_bgload) = frequency; |
306 | *((uint32_t*) qemu_icp_hw_map.rtc1_bgload) = frequency; |
| 305 | qemu_icp_irqc_mask(QEMU_ICP_TIMER_IRQ); |
- | |
| 306 | *((uint32_t*) qemu_icp_hw_map.rtc1_ctl) = QEMU_ICP_RTC_CTL_VALUE; |
307 | *((uint32_t*) qemu_icp_hw_map.rtc1_ctl) = QEMU_ICP_RTC_CTL_VALUE; |
| 307 | qemu_icp_irqc_unmask(QEMU_ICP_TIMER_IRQ); |
308 | qemu_icp_irqc_unmask(QEMU_ICP_TIMER_IRQ); |
| 308 | } |
309 | } |
| 309 | 310 | ||
| 310 | static irq_ownership_t qemu_icp_timer_claim(void) |
311 | static irq_ownership_t qemu_icp_timer_claim(void) |
| 311 | { |
312 | { |
| - | 313 | *((uint32_t*) qemu_icp_hw_map.rtc1_intrclr) = 1; |
|
| 312 | return IRQ_ACCEPT; |
314 | return IRQ_ACCEPT; |
| 313 | } |
315 | } |
| 314 | 316 | ||
| 315 | /** Timer interrupt handler. |
317 | /** Timer interrupt handler. |
| 316 | * |
318 | * |
| Line 325... | Line 327... | ||
| 325 | */ |
327 | */ |
| 326 | spinlock_unlock(&irq->lock); |
328 | spinlock_unlock(&irq->lock); |
| 327 | clock(); |
329 | clock(); |
| 328 | spinlock_lock(&irq->lock); |
330 | spinlock_lock(&irq->lock); |
| 329 | 331 | ||
| 330 | /* acknowledge tick */ |
- | |
| 331 | *((uint32_t*) qemu_icp_hw_map.rtc1_intrclr) = 0; |
- | |
| 332 | } |
332 | } |
| 333 | 333 | ||
| 334 | /** Initializes and registers timer interrupt handler. */ |
334 | /** Initializes and registers timer interrupt handler. */ |
| 335 | static void qemu_icp_timer_irq_init(void) |
335 | static void qemu_icp_timer_irq_init(void) |
| 336 | { |
336 | { |