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Rev 3759 Rev 4612
Line 50... Line 50...
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/* Addresses of devices. */
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/* Addresses of devices. */
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#define QEMU_ICP_VIDEORAM            0x16000000
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#define QEMU_ICP_VIDEORAM            0x16000000
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#define QEMU_ICP_KBD                 0x18000000
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#define QEMU_ICP_KBD                 0x18000000
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#define QEMU_ICP_HALT_OFFSET         0x10
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#define QEMU_ICP_HALT_OFFSET         0x10
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#define QEMU_ICP_RTC                 0x13000000
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#define QEMU_ICP_RTC                 0x13000000
- 
 
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#define QEMU_ICP_RTC1_LOAD_OFFSET    0x100
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#define QEMU_ICP_RTC_FREQ_OFFSET     0x100
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#define QEMU_ICP_RTC1_READ_OFFSET    0x104
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#define QEMU_ICP_RTC_ACK_OFFSET      0x110
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#define QEMU_ICP_RTC1_CTL_OFFSET     0x108
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#define QEMU_ICP_RTC1_INTRCLR_OFFSET 0x10C
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#define QEMU_ICP_RTC1_BGLOAD_OFFSET  0x118
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#define QEMU_ICP_RTC_CTL_VALUE       0x00E2
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#define QEMU_ICP_IRQC                0x14000000
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#define QEMU_ICP_IRQC                0x14000000
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#define QEMU_ICP_IRQC_MASK_OFFSET    0xC
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#define QEMU_ICP_IRQC_MASK_OFFSET    0xC
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#define QEMU_ICP_IRQC_UNMASK_OFFSET  0x8
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#define QEMU_ICP_IRQC_UNMASK_OFFSET  0x8
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#define QEMU_ICP_MP                  0x11000000
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#define QEMU_ICP_MP                  0x11000000
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#define QEMU_ICP_MP_MEMSIZE_OFFSET   0x0090
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#define QEMU_ICP_MP_MEMSIZE_OFFSET   0x0090
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 67 
 
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#define ICP_VGA              0xC0000000
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#define ICP_VGA              0xC0000000
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#define ICP_CMCR             0x10000000
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#define ICP_CMCR             0x10000000
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/* IRQs */
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/* IRQs */
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#define QEMU_ICP_KBD_IRQ        0x03
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#define QEMU_ICP_KBD_IRQ        3
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#define QEMU_ICP_TIMER_IRQ      0x05
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#define QEMU_ICP_TIMER_IRQ      6
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71 
static qemu_icp_hw_map_t qemu_icp_hw_map;
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static qemu_icp_hw_map_t qemu_icp_hw_map;
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static chardev_t console;
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static chardev_t console;
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static irq_t qemu_icp_console_irq;
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static irq_t qemu_icp_console_irq;
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static irq_t qemu_icp_timer_irq;
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static irq_t qemu_icp_timer_irq;
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 *
 120 
 *
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 * @param irq interrupt number
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 * @param irq interrupt number
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 */
 122 
 */
119 
static inline void qemu_icp_irqc_mask(uint32_t irq)
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static inline void qemu_icp_irqc_mask(uint32_t irq)
120 
{
 124 
{
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    *((uint32_t *) qemu_icp_hw_map.irqc_mask) = irq;
 125 
    *((uint32_t *) qemu_icp_hw_map.irqc_mask) = (1 << irq);
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}
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}
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 127 
 
124 
 
 128 
 
125 
/** Unmasks interrupt.
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/** Unmasks interrupt.
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 *
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 *
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 * @param irq interrupt number
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 * @param irq interrupt number
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 */
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 */
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static inline void qemu_icp_irqc_unmask(uint32_t irq)
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static inline void qemu_icp_irqc_unmask(uint32_t irq)
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{
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{
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    *((uint32_t *) qemu_icp_hw_map.irqc_unmask) |= irq;
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    *((uint32_t *) qemu_icp_hw_map.irqc_unmask) |= (1 << irq);
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}
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}
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/** Initializes the icp frame buffer */
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/** Initializes the icp frame buffer */
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void qemu_icp_fb_init(void)
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void qemu_icp_fb_init(void)
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{
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{
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void qemu_icp_hw_map_init(void)
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void qemu_icp_hw_map_init(void)
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{
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{
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    qemu_icp_hw_map.videoram = hw_map(QEMU_ICP_VIDEORAM, PAGE_SIZE);
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    qemu_icp_hw_map.videoram = hw_map(QEMU_ICP_VIDEORAM, PAGE_SIZE);
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    qemu_icp_hw_map.kbd = hw_map(QEMU_ICP_KBD, PAGE_SIZE);
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    qemu_icp_hw_map.kbd = hw_map(QEMU_ICP_KBD, PAGE_SIZE);
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    qemu_icp_hw_map.rtc = hw_map(QEMU_ICP_RTC, PAGE_SIZE);
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    qemu_icp_hw_map.rtc = hw_map(QEMU_ICP_RTC, PAGE_SIZE);
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    qemu_icp_hw_map.rtc1_load = qemu_icp_hw_map.rtc + QEMU_ICP_RTC1_LOAD_OFFSET;
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    qemu_icp_hw_map.rtc1_read = qemu_icp_hw_map.rtc + QEMU_ICP_RTC1_READ_OFFSET;
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    qemu_icp_hw_map.irqc = hw_map(QEMU_ICP_IRQC, PAGE_SIZE);
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    qemu_icp_hw_map.rtc1_ctl = qemu_icp_hw_map.rtc + QEMU_ICP_RTC1_CTL_OFFSET;
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    qemu_icp_hw_map.rtc1_intrclr = qemu_icp_hw_map.rtc + QEMU_ICP_RTC1_INTRCLR_OFFSET;
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    qemu_icp_hw_map.rtc1_bgload = qemu_icp_hw_map.rtc + QEMU_ICP_RTC1_BGLOAD_OFFSET;
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    qemu_icp_hw_map.rtc_freq = qemu_icp_hw_map.rtc + QEMU_ICP_RTC_FREQ_OFFSET;
 - 
 
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    qemu_icp_hw_map.rtc_ack = qemu_icp_hw_map.rtc + QEMU_ICP_RTC_ACK_OFFSET;
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    qemu_icp_hw_map.irqc = hw_map(QEMU_ICP_IRQC, PAGE_SIZE);
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    qemu_icp_hw_map.irqc_mask = qemu_icp_hw_map.irqc + QEMU_ICP_IRQC_MASK_OFFSET;
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    qemu_icp_hw_map.irqc_mask = qemu_icp_hw_map.irqc + QEMU_ICP_IRQC_MASK_OFFSET;
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    qemu_icp_hw_map.irqc_unmask = qemu_icp_hw_map.irqc +
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    qemu_icp_hw_map.irqc_unmask = qemu_icp_hw_map.irqc +
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        QEMU_ICP_IRQC_UNMASK_OFFSET;
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        QEMU_ICP_IRQC_UNMASK_OFFSET;
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    qemu_icp_hw_map.cmcr = hw_map(ICP_CMCR, PAGE_SIZE);
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    qemu_icp_hw_map.cmcr = hw_map(ICP_CMCR, PAGE_SIZE);
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    qemu_icp_hw_map.vga = hw_map(ICP_VGA, PAGE_SIZE);
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    qemu_icp_hw_map.vga = hw_map(ICP_VGA, PAGE_SIZE);
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 *
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 *
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 * @param frequency Interrupts frequency (0 disables RTC).
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 * @param frequency Interrupts frequency (0 disables RTC).
293 
 */
 300 
 */
294 
static void qemu_icp_timer_start(uint32_t frequency)
 301 
static void qemu_icp_timer_start(uint32_t frequency)
295 
{
 302 
{
296 
    *((uint32_t*) qemu_icp_hw_map.rtc_freq) = frequency;
 303 
    *((uint32_t*) qemu_icp_hw_map.rtc1_load) = frequency;
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 304 
    *((uint32_t*) qemu_icp_hw_map.rtc1_bgload) = frequency;
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 305 
    qemu_icp_irqc_mask(QEMU_ICP_TIMER_IRQ);
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 306 
    *((uint32_t*) qemu_icp_hw_map.rtc1_ctl) = QEMU_ICP_RTC_CTL_VALUE;
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 307 
    qemu_icp_irqc_unmask(QEMU_ICP_TIMER_IRQ);
297 
}
 308 
}
298 
 
 309 
 
299 
static irq_ownership_t qemu_icp_timer_claim(void)
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static irq_ownership_t qemu_icp_timer_claim(void)
300 
{
 311 
{
301 
    return IRQ_ACCEPT;
 312 
    return IRQ_ACCEPT;
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    spinlock_unlock(&irq->lock);
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    spinlock_unlock(&irq->lock);
316 
    clock();
 327 
    clock();
317 
    spinlock_lock(&irq->lock);
 328 
    spinlock_lock(&irq->lock);
318 
 
 329 
 
319 
    /* acknowledge tick */
 330 
    /* acknowledge tick */
320 
    *((uint32_t*) qemu_icp_hw_map.rtc_ack) = 0;
 331 
    *((uint32_t*) qemu_icp_hw_map.rtc1_intrclr) = 0;
321 
}
 332 
}
322 
 
 333 
 
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/** Initializes and registers timer interrupt handler. */
 334 
/** Initializes and registers timer interrupt handler. */
324 
static void qemu_icp_timer_irq_init(void)
 335 
static void qemu_icp_timer_irq_init(void)
325 
{
 336 
{