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Line 38... | Line 38... | ||
38 | 38 | ||
39 | #include <arch/mm/frame.h> |
39 | #include <arch/mm/frame.h> |
40 | #include <mm/mm.h> |
40 | #include <mm/mm.h> |
41 | #include <arch/exception.h> |
41 | #include <arch/exception.h> |
42 | 42 | ||
43 | - | ||
44 | #define PAGE_WIDTH FRAME_WIDTH |
43 | #define PAGE_WIDTH FRAME_WIDTH |
45 | #define PAGE_SIZE FRAME_SIZE |
44 | #define PAGE_SIZE FRAME_SIZE |
46 | 45 | ||
47 | #define PAGE_COLOR_BITS 0 /* dummy */ |
46 | #define PAGE_COLOR_BITS 0 /* dummy */ |
48 | 47 | ||
Line 54... | Line 53... | ||
54 | # define PA2KA(x) ((x) + 0x80000000) |
53 | # define PA2KA(x) ((x) + 0x80000000) |
55 | #endif |
54 | #endif |
56 | 55 | ||
57 | #ifdef KERNEL |
56 | #ifdef KERNEL |
58 | 57 | ||
59 | #define PTL0_ENTRIES_ARCH (2<<12) // 4096 |
58 | #define PTL0_ENTRIES_ARCH (2 << 12) /* 4096 */ |
60 | #define PTL1_ENTRIES_ARCH 0 |
59 | #define PTL1_ENTRIES_ARCH 0 |
61 | #define PTL2_ENTRIES_ARCH 0 |
60 | #define PTL2_ENTRIES_ARCH 0 |
62 | 61 | ||
63 | /* coarse page tables used (256*4 = 1KB per page) */ |
62 | /* coarse page tables used (256 * 4 = 1KB per page) */ |
64 | #define PTL3_ENTRIES_ARCH (2<<8) // 256 |
63 | #define PTL3_ENTRIES_ARCH (2 << 8) /* 256 */ |
65 | 64 | ||
66 | #define PTL0_SIZE_ARCH FOUR_FRAMES |
65 | #define PTL0_SIZE_ARCH FOUR_FRAMES |
67 | #define PTL1_SIZE_ARCH 0 |
66 | #define PTL1_SIZE_ARCH 0 |
68 | #define PTL2_SIZE_ARCH 0 |
67 | #define PTL2_SIZE_ARCH 0 |
69 | #define PTL3_SIZE_ARCH ONE_FRAME |
68 | #define PTL3_SIZE_ARCH ONE_FRAME |
Line 71... | Line 70... | ||
71 | #define PTL0_INDEX_ARCH(vaddr) (((vaddr) >> 20) & 0xfff) |
70 | #define PTL0_INDEX_ARCH(vaddr) (((vaddr) >> 20) & 0xfff) |
72 | #define PTL1_INDEX_ARCH(vaddr) 0 |
71 | #define PTL1_INDEX_ARCH(vaddr) 0 |
73 | #define PTL2_INDEX_ARCH(vaddr) 0 |
72 | #define PTL2_INDEX_ARCH(vaddr) 0 |
74 | #define PTL3_INDEX_ARCH(vaddr) (((vaddr) >> 12) & 0x0ff) |
73 | #define PTL3_INDEX_ARCH(vaddr) (((vaddr) >> 12) & 0x0ff) |
75 | 74 | ||
- | 75 | #define GET_PTL1_ADDRESS_ARCH(ptl0, i) \ |
|
76 | #define GET_PTL1_ADDRESS_ARCH(ptl0, i) ((pte_t *)( (((pte_level0_t*)(ptl0))[(i)]).coarse_table_addr << 10 )) |
76 | ((pte_t *) ((((pte_level0_t *)(ptl0))[(i)]).coarse_table_addr << 10)) |
77 | #define GET_PTL2_ADDRESS_ARCH(ptl1, i) (ptl1) |
77 | #define GET_PTL2_ADDRESS_ARCH(ptl1, i) \ |
- | 78 | (ptl1) |
|
78 | #define GET_PTL3_ADDRESS_ARCH(ptl2, i) (ptl2) |
79 | #define GET_PTL3_ADDRESS_ARCH(ptl2, i) \ |
- | 80 | (ptl2) |
|
- | 81 | #define GET_FRAME_ADDRESS_ARCH(ptl3, i) \ |
|
79 | #define GET_FRAME_ADDRESS_ARCH(ptl3, i) ((uintptr_t)( (((pte_level1_t*)(ptl3))[(i)]).frame_base_addr << 12 )) |
82 | ((uintptr_t) ((((pte_level1_t *)(ptl3))[(i)]).frame_base_addr << 12)) |
80 | 83 | ||
- | 84 | #define SET_PTL0_ADDRESS_ARCH(ptl0) \ |
|
81 | #define SET_PTL0_ADDRESS_ARCH(ptl0) (set_ptl0_addr((pte_level0_t *)(ptl0))) |
85 | (set_ptl0_addr((pte_level0_t *) (ptl0))) |
- | 86 | #define SET_PTL1_ADDRESS_ARCH(ptl0, i, a) \ |
|
82 | #define SET_PTL1_ADDRESS_ARCH(ptl0, i, a) (((pte_level0_t *)(ptl0))[(i)].coarse_table_addr = (a)>>10) |
87 | (((pte_level0_t *) (ptl0))[(i)].coarse_table_addr = (a) >> 10) |
83 | #define SET_PTL2_ADDRESS_ARCH(ptl1, i, a) |
88 | #define SET_PTL2_ADDRESS_ARCH(ptl1, i, a) |
84 | #define SET_PTL3_ADDRESS_ARCH(ptl2, i, a) |
89 | #define SET_PTL3_ADDRESS_ARCH(ptl2, i, a) |
- | 90 | #define SET_FRAME_ADDRESS_ARCH(ptl3, i, a) \ |
|
85 | #define SET_FRAME_ADDRESS_ARCH(ptl3, i, a) (((pte_level1_t *)(ptl3))[(i)].frame_base_addr = (a)>>12) |
91 | (((pte_level1_t *) (ptl3))[(i)].frame_base_addr = (a) >> 12) |
86 | 92 | ||
- | 93 | #define GET_PTL1_FLAGS_ARCH(ptl0, i) \ |
|
87 | #define GET_PTL1_FLAGS_ARCH(ptl0, i) get_pt_level0_flags((pte_level0_t *)(ptl0), (index_t)(i)) |
94 | get_pt_level0_flags((pte_level0_t *) (ptl0), (index_t) (i)) |
88 | #define GET_PTL2_FLAGS_ARCH(ptl1, i) PAGE_PRESENT |
95 | #define GET_PTL2_FLAGS_ARCH(ptl1, i) \ |
- | 96 | PAGE_PRESENT |
|
89 | #define GET_PTL3_FLAGS_ARCH(ptl2, i) PAGE_PRESENT |
97 | #define GET_PTL3_FLAGS_ARCH(ptl2, i) \ |
- | 98 | PAGE_PRESENT |
|
- | 99 | #define GET_FRAME_FLAGS_ARCH(ptl3, i) \ |
|
90 | #define GET_FRAME_FLAGS_ARCH(ptl3, i) get_pt_level1_flags((pte_level1_t *)(ptl3), (index_t)(i)) |
100 | get_pt_level1_flags((pte_level1_t *) (ptl3), (index_t) (i)) |
91 | 101 | ||
- | 102 | #define SET_PTL1_FLAGS_ARCH(ptl0, i, x) \ |
|
92 | #define SET_PTL1_FLAGS_ARCH(ptl0, i, x) set_pt_level0_flags((pte_level0_t *)(ptl0), (index_t)(i), (x)) |
103 | set_pt_level0_flags((pte_level0_t *) (ptl0), (index_t) (i), (x)) |
93 | #define SET_PTL2_FLAGS_ARCH(ptl1, i, x) |
104 | #define SET_PTL2_FLAGS_ARCH(ptl1, i, x) |
94 | #define SET_PTL3_FLAGS_ARCH(ptl2, i, x) |
105 | #define SET_PTL3_FLAGS_ARCH(ptl2, i, x) |
- | 106 | #define SET_FRAME_FLAGS_ARCH(ptl3, i, x) \ |
|
95 | #define SET_FRAME_FLAGS_ARCH(ptl3, i, x) set_pt_level1_flags((pte_level1_t *)(ptl3), (index_t)(i), (x)) |
107 | set_pt_level1_flags((pte_level1_t *) (ptl3), (index_t) (i), (x)) |
96 | 108 | ||
- | 109 | #define PTE_VALID_ARCH(pte) \ |
|
97 | #define PTE_VALID_ARCH(pte) (*((uint32_t *) (pte)) != 0) |
110 | (*((uint32_t *) (pte)) != 0) |
- | 111 | #define PTE_PRESENT_ARCH(pte) \ |
|
98 | #define PTE_PRESENT_ARCH(pte) ( ((pte_level0_t *)(pte))->descriptor_type != 0 ) |
112 | (((pte_level0_t *) (pte))->descriptor_type != 0) |
99 | 113 | ||
100 | /* pte should point into ptl3 */ |
114 | /* pte should point into ptl3 */ |
- | 115 | #define PTE_GET_FRAME_ARCH(pte) \ |
|
101 | #define PTE_GET_FRAME_ARCH(pte) ( ((pte_level1_t *)(pte))->frame_base_addr << FRAME_WIDTH) |
116 | (((pte_level1_t *) (pte))->frame_base_addr << FRAME_WIDTH) |
102 | 117 | ||
103 | /* pte should point into ptl3 */ |
118 | /* pte should point into ptl3 */ |
- | 119 | #define PTE_WRITABLE_ARCH(pte) \ |
|
104 | #define PTE_WRITABLE_ARCH(pte) ( ((pte_level1_t *)(pte))->access_permission_0 == PTE_AP_USER_RW_KERNEL_RW ) |
120 | (((pte_level1_t *) (pte))->access_permission_0 == \ |
105 | - | ||
106 | #define PTE_EXECUTABLE_ARCH(pte) 1 |
121 | PTE_AP_USER_RW_KERNEL_RW) |
107 | 122 | ||
- | 123 | #define PTE_EXECUTABLE_ARCH(pte) \ |
|
- | 124 | 1 |
|
108 | 125 | ||
109 | #ifndef __ASM__ |
126 | #ifndef __ASM__ |
110 | 127 | ||
111 | /** Level 0 page table entry. */ |
128 | /** Level 0 page table entry. */ |
112 | typedef struct { |
129 | typedef struct { |
113 | - | ||
114 | /* 01b for coarse tables, see below for details */ |
130 | /* 0b01 for coarse tables, see below for details */ |
115 | unsigned descriptor_type : 2; |
131 | unsigned descriptor_type : 2; |
116 | unsigned impl_specific : 3; |
132 | unsigned impl_specific : 3; |
117 | unsigned domain : 4; |
133 | unsigned domain : 4; |
118 | unsigned should_be_zero : 1; |
134 | unsigned should_be_zero : 1; |
119 | 135 | ||
120 | /* Pointer to the coarse 2nd level page table (holding entries for small (4KB) |
136 | /* Pointer to the coarse 2nd level page table (holding entries for small |
121 | * or large (64KB) pages. ARM also supports fine 2nd level page tables that |
137 | * (4KB) or large (64KB) pages. ARM also supports fine 2nd level page |
122 | * may hold even tiny pages (1KB) but they are bigger (4KB per table in comparison |
138 | * tables that may hold even tiny pages (1KB) but they are bigger (4KB |
123 | * with 1KB per the coarse table) |
139 | * per table in comparison with 1KB per the coarse table) |
124 | */ |
140 | */ |
125 | unsigned coarse_table_addr : 22; |
141 | unsigned coarse_table_addr : 22; |
126 | } ATTRIBUTE_PACKED pte_level0_t; |
142 | } ATTRIBUTE_PACKED pte_level0_t; |
127 | 143 | ||
128 | - | ||
129 | /** Level 1 page table entry (small (4KB) pages used). */ |
144 | /** Level 1 page table entry (small (4KB) pages used). */ |
130 | typedef struct { |
145 | typedef struct { |
131 | 146 | ||
132 | /* 0b10 for small pages */ |
147 | /* 0b10 for small pages */ |
133 | unsigned descriptor_type : 2; |
148 | unsigned descriptor_type : 2; |
Line 145... | Line 160... | ||
145 | 160 | ||
146 | 161 | ||
147 | /* Level 1 page tables access permissions */ |
162 | /* Level 1 page tables access permissions */ |
148 | 163 | ||
149 | /** User mode: no access, privileged mode: no access. */ |
164 | /** User mode: no access, privileged mode: no access. */ |
150 | #define PTE_AP_USER_NO_KERNEL_NO 0 |
165 | #define PTE_AP_USER_NO_KERNEL_NO 0 |
151 | 166 | ||
152 | /** User mode: no access, privileged mode: read/write. */ |
167 | /** User mode: no access, privileged mode: read/write. */ |
153 | #define PTE_AP_USER_NO_KERNEL_RW 1 |
168 | #define PTE_AP_USER_NO_KERNEL_RW 1 |
154 | 169 | ||
155 | /** User mode: read only, privileged mode: read/write. */ |
170 | /** User mode: read only, privileged mode: read/write. */ |
156 | #define PTE_AP_USER_RO_KERNEL_RW 2 |
171 | #define PTE_AP_USER_RO_KERNEL_RW 2 |
157 | 172 | ||
158 | /** User mode: read/write, privileged mode: read/write. */ |
173 | /** User mode: read/write, privileged mode: read/write. */ |
159 | #define PTE_AP_USER_RW_KERNEL_RW 3 |
174 | #define PTE_AP_USER_RW_KERNEL_RW 3 |
160 | 175 | ||
161 | 176 | ||
162 | /* pte_level0_t and pte_level1_t descriptor_type flags */ |
177 | /* pte_level0_t and pte_level1_t descriptor_type flags */ |
163 | 178 | ||
164 | /** pte_level0_t and pte_level1_t "not present" flag (used in descriptor_type). */ |
179 | /** pte_level0_t and pte_level1_t "not present" flag (used in descriptor_type). */ |
165 | #define PTE_DESCRIPTOR_NOT_PRESENT 0 |
180 | #define PTE_DESCRIPTOR_NOT_PRESENT 0 |
166 | 181 | ||
167 | /** pte_level0_t coarse page table flag (used in descriptor_type). */ |
182 | /** pte_level0_t coarse page table flag (used in descriptor_type). */ |
168 | #define PTE_DESCRIPTOR_COARSE_TABLE 1 |
183 | #define PTE_DESCRIPTOR_COARSE_TABLE 1 |
169 | 184 | ||
170 | /** pte_level1_t small page table flag (used in descriptor type). */ |
185 | /** pte_level1_t small page table flag (used in descriptor type). */ |
171 | #define PTE_DESCRIPTOR_SMALL_PAGE 2 |
186 | #define PTE_DESCRIPTOR_SMALL_PAGE 2 |
172 | 187 | ||
173 | 188 | ||
174 | /** Sets the address of level 0 page table. |
189 | /** Sets the address of level 0 page table. |
175 | * |
190 | * |
176 | * @param pt Pointer to the page table to set. |
191 | * @param pt Pointer to the page table to set. |
177 | */ |
192 | */ |
178 | static inline void set_ptl0_addr( pte_level0_t* pt) |
193 | static inline void set_ptl0_addr( pte_level0_t *pt) |
179 | { |
194 | { |
180 | asm volatile ( |
195 | asm volatile ( |
181 | "mcr p15, 0, %0, c2, c0, 0 \n" |
196 | "mcr p15, 0, %0, c2, c0, 0 \n" |
182 | : |
197 | : |
183 | : "r"(pt) |
198 | : "r"(pt) |
Line 191... | Line 206... | ||
191 | * @param i Index of the entry to return. |
206 | * @param i Index of the entry to return. |
192 | */ |
207 | */ |
193 | static inline int get_pt_level0_flags(pte_level0_t *pt, index_t i) |
208 | static inline int get_pt_level0_flags(pte_level0_t *pt, index_t i) |
194 | { |
209 | { |
195 | pte_level0_t *p = &pt[i]; |
210 | pte_level0_t *p = &pt[i]; |
- | 211 | int np = (p->descriptor_type == PTE_DESCRIPTOR_NOT_PRESENT); |
|
196 | 212 | ||
197 | return |
- | |
198 | ( (p->descriptor_type == PTE_DESCRIPTOR_NOT_PRESENT) << PAGE_PRESENT_SHIFT ) | |
213 | return (np << PAGE_PRESENT_SHIFT) | (1 << PAGE_USER_SHIFT) | |
199 | ( 1 << PAGE_USER_SHIFT ) | |
- | |
200 | ( 1 << PAGE_READ_SHIFT ) | |
214 | (1 << PAGE_READ_SHIFT) | (1 << PAGE_WRITE_SHIFT) | |
201 | ( 1 << PAGE_WRITE_SHIFT ) | |
- | |
202 | ( 1 << PAGE_EXEC_SHIFT ) | |
- | |
203 | ( 1 << PAGE_CACHEABLE_SHIFT ) |
215 | (1 << PAGE_EXEC_SHIFT) | (1 << PAGE_CACHEABLE_SHIFT); |
204 | ; |
- | |
205 | } |
216 | } |
206 | 217 | ||
207 | - | ||
208 | /** Returns level 1 page table entry flags. |
218 | /** Returns level 1 page table entry flags. |
209 | * |
219 | * |
210 | * @param pt Level 1 page table. |
220 | * @param pt Level 1 page table. |
211 | * @param i Index of the entry to return. |
221 | * @param i Index of the entry to return. |
212 | */ |
222 | */ |
213 | static inline int get_pt_level1_flags(pte_level1_t *pt, index_t i) |
223 | static inline int get_pt_level1_flags(pte_level1_t *pt, index_t i) |
214 | { |
224 | { |
215 | pte_level1_t *p = &pt[i]; |
225 | pte_level1_t *p = &pt[i]; |
216 | 226 | ||
217 | return |
227 | int dt = p->descriptor_type; |
- | 228 | int ap = p->access_permission_0; |
|
- | 229 | ||
218 | ( (p->descriptor_type == PTE_DESCRIPTOR_NOT_PRESENT) << PAGE_PRESENT_SHIFT) | |
230 | return ((dt == PTE_DESCRIPTOR_NOT_PRESENT) << PAGE_PRESENT_SHIFT) | |
219 | ( (p->access_permission_0 == PTE_AP_USER_RO_KERNEL_RW) << PAGE_READ_SHIFT ) | |
231 | ((ap == PTE_AP_USER_RO_KERNEL_RW) << PAGE_READ_SHIFT) | |
220 | ( (p->access_permission_0 == PTE_AP_USER_RW_KERNEL_RW) << PAGE_READ_SHIFT ) | |
232 | ((ap == PTE_AP_USER_RW_KERNEL_RW) << PAGE_READ_SHIFT) | |
221 | ( (p->access_permission_0 == PTE_AP_USER_RW_KERNEL_RW) << PAGE_WRITE_SHIFT ) | |
233 | ((ap == PTE_AP_USER_RW_KERNEL_RW) << PAGE_WRITE_SHIFT) | |
222 | ( (p->access_permission_0 != PTE_AP_USER_NO_KERNEL_RW) << PAGE_USER_SHIFT ) | |
234 | ((ap != PTE_AP_USER_NO_KERNEL_RW) << PAGE_USER_SHIFT) | |
223 | ( (p->access_permission_0 == PTE_AP_USER_NO_KERNEL_RW) << PAGE_READ_SHIFT ) | |
235 | ((ap == PTE_AP_USER_NO_KERNEL_RW) << PAGE_READ_SHIFT) | |
224 | ( (p->access_permission_0 == PTE_AP_USER_NO_KERNEL_RW) << PAGE_WRITE_SHIFT ) | |
236 | ((ap == PTE_AP_USER_NO_KERNEL_RW) << PAGE_WRITE_SHIFT) | |
225 | ( 1 << PAGE_EXEC_SHIFT ) | |
237 | (1 << PAGE_EXEC_SHIFT) | |
226 | ( p->bufferable << PAGE_CACHEABLE ) |
238 | (p->bufferable << PAGE_CACHEABLE); |
227 | ; |
- | |
228 | } |
239 | } |
229 | 240 | ||
230 | 241 | ||
231 | /** Sets flags of level 0 page table entry. |
242 | /** Sets flags of level 0 page table entry. |
232 | * |
243 | * |
Line 238... | Line 249... | ||
238 | { |
249 | { |
239 | pte_level0_t *p = &pt[i]; |
250 | pte_level0_t *p = &pt[i]; |
240 | 251 | ||
241 | if (flags & PAGE_NOT_PRESENT) { |
252 | if (flags & PAGE_NOT_PRESENT) { |
242 | p->descriptor_type = PTE_DESCRIPTOR_NOT_PRESENT; |
253 | p->descriptor_type = PTE_DESCRIPTOR_NOT_PRESENT; |
- | 254 | /* |
|
243 | // ensures that the entry will be recognized as valid when PTE_VALID_ARCH applied |
255 | * Ensures that the entry will be recognized as valid when |
- | 256 | * PTE_VALID_ARCH applied. |
|
- | 257 | */ |
|
244 | p->should_be_zero = 1; |
258 | p->should_be_zero = 1; |
245 | } else { |
259 | } else { |
246 | p->descriptor_type = PTE_DESCRIPTOR_COARSE_TABLE; |
260 | p->descriptor_type = PTE_DESCRIPTOR_COARSE_TABLE; |
247 | p->should_be_zero = 0; |
261 | p->should_be_zero = 0; |
248 | } |
262 | } |
249 | } |
263 | } |
250 | 264 | ||
251 | 265 | ||
252 | /** Sets flags of level 1 page table entry. |
266 | /** Sets flags of level 1 page table entry. |
Line 262... | Line 276... | ||
262 | static inline void set_pt_level1_flags(pte_level1_t *pt, index_t i, int flags) |
276 | static inline void set_pt_level1_flags(pte_level1_t *pt, index_t i, int flags) |
263 | { |
277 | { |
264 | pte_level1_t *p = &pt[i]; |
278 | pte_level1_t *p = &pt[i]; |
265 | 279 | ||
266 | if (flags & PAGE_NOT_PRESENT) { |
280 | if (flags & PAGE_NOT_PRESENT) { |
267 | p->descriptor_type = PTE_DESCRIPTOR_NOT_PRESENT; |
281 | p->descriptor_type = PTE_DESCRIPTOR_NOT_PRESENT; |
268 | p->access_permission_3 = 1; |
282 | p->access_permission_3 = 1; |
269 | } else { |
283 | } else { |
270 | p->descriptor_type = PTE_DESCRIPTOR_SMALL_PAGE; |
284 | p->descriptor_type = PTE_DESCRIPTOR_SMALL_PAGE; |
271 | p->access_permission_3 = p->access_permission_0; |
285 | p->access_permission_3 = p->access_permission_0; |
272 | } |
286 | } |
273 | 287 | ||
274 | p->cacheable = p->bufferable = (flags & PAGE_CACHEABLE) != 0; |
288 | p->cacheable = p->bufferable = (flags & PAGE_CACHEABLE) != 0; |
275 | 289 | ||
276 | /* default access permission */ |
290 | /* default access permission */ |
277 | p->access_permission_0 = p->access_permission_1 = |
291 | p->access_permission_0 = p->access_permission_1 = |
278 | p->access_permission_2 = p->access_permission_3 = PTE_AP_USER_NO_KERNEL_RW; |
292 | p->access_permission_2 = p->access_permission_3 = |
- | 293 | PTE_AP_USER_NO_KERNEL_RW; |
|
279 | 294 | ||
280 | if (flags & PAGE_USER) { |
295 | if (flags & PAGE_USER) { |
281 | if (flags & PAGE_READ) { |
296 | if (flags & PAGE_READ) { |
282 | p->access_permission_0 = p->access_permission_1 = |
297 | p->access_permission_0 = p->access_permission_1 = |
283 | p->access_permission_2 = p->access_permission_3 = |
298 | p->access_permission_2 = p->access_permission_3 = |
284 | PTE_AP_USER_RO_KERNEL_RW; |
299 | PTE_AP_USER_RO_KERNEL_RW; |
285 | } |
300 | } |
286 | if (flags & PAGE_WRITE) { |
301 | if (flags & PAGE_WRITE) { |
287 | p->access_permission_0 = p->access_permission_1 = |
302 | p->access_permission_0 = p->access_permission_1 = |
288 | p->access_permission_2 = p->access_permission_3 = |
303 | p->access_permission_2 = p->access_permission_3 = |
289 | PTE_AP_USER_RW_KERNEL_RW; |
304 | PTE_AP_USER_RW_KERNEL_RW; |
290 | } |
305 | } |
291 | } |
306 | } |
292 | } |
307 | } |
293 | 308 | ||
294 | 309 | ||
Line 301... | Line 316... | ||
301 | 316 | ||
302 | #endif |
317 | #endif |
303 | 318 | ||
304 | /** @} |
319 | /** @} |
305 | */ |
320 | */ |
306 | - |