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#   define PA2KA(x) ((x) + 0x80000000)
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#   define PA2KA(x) ((x) + 0x80000000)
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#endif
 54 
#endif
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 55 
 
56 
#ifdef KERNEL
 56 
#ifdef KERNEL
57 
 
 57 
 
58 
#define PTL0_ENTRIES_ARCH    (2<<12)    // 4096
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#define PTL0_ENTRIES_ARCH   (2<<12)    // 4096
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#define PTL1_ENTRIES_ARCH     0
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#define PTL1_ENTRIES_ARCH   0
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#define PTL2_ENTRIES_ARCH     0
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#define PTL2_ENTRIES_ARCH   0
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/* coarse page tables used (256*4 = 1KB per page) */
 61 
/* coarse page tables used (256*4 = 1KB per page) */
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#define PTL3_ENTRIES_ARCH    (2<<8)     // 256
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#define PTL3_ENTRIES_ARCH   (2<<8)     // 256
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 63 
 
64 
#define PTL0_SIZE_ARCH       FOUR_FRAMES
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#define PTL0_SIZE_ARCH      FOUR_FRAMES
65 
#define PTL1_SIZE_ARCH       0
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#define PTL1_SIZE_ARCH      0
66 
#define PTL2_SIZE_ARCH       0
 66 
#define PTL2_SIZE_ARCH      0
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#define PTL3_SIZE_ARCH       ONE_FRAME
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#define PTL3_SIZE_ARCH      ONE_FRAME
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 68 
 
69 
#define PTL0_INDEX_ARCH(vaddr)    (((vaddr) >> 20) & 0xfff)
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#define PTL0_INDEX_ARCH(vaddr)  (((vaddr) >> 20) & 0xfff)
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#define PTL1_INDEX_ARCH(vaddr)    0
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#define PTL1_INDEX_ARCH(vaddr)  0
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#define PTL2_INDEX_ARCH(vaddr)    0
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#define PTL2_INDEX_ARCH(vaddr)  0
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#define PTL3_INDEX_ARCH(vaddr)    (((vaddr) >> 12) & 0x0ff)
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#define PTL3_INDEX_ARCH(vaddr)  (((vaddr) >> 12) & 0x0ff)
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 73 
 
74 
#define GET_PTL1_ADDRESS_ARCH(ptl0, i)      ((pte_t *)( (((pte_level0_t*)(ptl0))[(i)]).coarse_table_addr << 10 ))
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#define GET_PTL1_ADDRESS_ARCH(ptl0, i)      ((pte_t *)( (((pte_level0_t*)(ptl0))[(i)]).coarse_table_addr << 10 ))
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#define GET_PTL2_ADDRESS_ARCH(ptl1, i)      (ptl1)
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#define GET_PTL2_ADDRESS_ARCH(ptl1, i)      (ptl1)
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#define GET_PTL3_ADDRESS_ARCH(ptl2, i)      (ptl2)
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#define GET_PTL3_ADDRESS_ARCH(ptl2, i)      (ptl2)
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#define GET_FRAME_ADDRESS_ARCH(ptl3, i)     ((uintptr_t)( (((pte_level1_t*)(ptl3))[(i)]).frame_base_addr << 12 ))
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#define GET_FRAME_ADDRESS_ARCH(ptl3, i)     ((uintptr_t)( (((pte_level1_t*)(ptl3))[(i)]).frame_base_addr << 12 ))
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79 
#define SET_PTL0_ADDRESS_ARCH(ptl0)         (set_ptl0_addr((pte_level0_t *)(ptl0)))
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#define SET_PTL0_ADDRESS_ARCH(ptl0)         (set_ptl0_addr((pte_level0_t *)(ptl0)))
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#define SET_PTL1_ADDRESS_ARCH(ptl0, i, a)   (((pte_level0_t *)(ptl0))[(i)].coarse_table_addr = (a)>>10)
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#define SET_PTL1_ADDRESS_ARCH(ptl0, i, a)   (((pte_level0_t *)(ptl0))[(i)].coarse_table_addr = (a)>>10)
81 
#define SET_PTL2_ADDRESS_ARCH(ptl1, i, a)
 81 
#define SET_PTL2_ADDRESS_ARCH(ptl1, i, a)
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#define SET_PTL3_ADDRESS_ARCH(ptl2, i, a)
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#define SET_PTL3_ADDRESS_ARCH(ptl2, i, a)
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#define SET_FRAME_ADDRESS_ARCH(ptl3, i, a)  (((pte_level1_t *)(ptl3))[(i)].frame_base_addr = (a)>>12)
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#define SET_FRAME_ADDRESS_ARCH(ptl3, i, a)  (((pte_level1_t *)(ptl3))[(i)].frame_base_addr = (a)>>12)
84 
 
 84 
 
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#define GET_PTL1_FLAGS_ARCH(ptl0, i)        get_pt_level0_flags((pte_level0_t *)(ptl0), (index_t)(i))
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#define GET_PTL1_FLAGS_ARCH(ptl0, i)        get_pt_level0_flags((pte_level0_t *)(ptl0), (index_t)(i))
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#define GET_PTL2_FLAGS_ARCH(ptl1, i)        PAGE_PRESENT
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#define GET_PTL2_FLAGS_ARCH(ptl1, i)        PAGE_PRESENT
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#define GET_PTL3_FLAGS_ARCH(ptl2, i)        PAGE_PRESENT
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#define GET_PTL3_FLAGS_ARCH(ptl2, i)        PAGE_PRESENT
88 
#define GET_FRAME_FLAGS_ARCH(ptl3, i)       get_pt_level1_flags((pte_level1_t *)(ptl3), (index_t)(i))
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#define GET_FRAME_FLAGS_ARCH(ptl3, i)       get_pt_level1_flags((pte_level1_t *)(ptl3), (index_t)(i))
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 89 
 
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#define SET_PTL1_FLAGS_ARCH(ptl0, i, x)     set_pt_level0_flags((pte_level0_t *)(ptl0), (index_t)(i), (x))
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#define SET_PTL1_FLAGS_ARCH(ptl0, i, x)     set_pt_level0_flags((pte_level0_t *)(ptl0), (index_t)(i), (x))
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#define SET_PTL2_FLAGS_ARCH(ptl1, i, x)
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#define SET_PTL2_FLAGS_ARCH(ptl1, i, x)
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#define SET_PTL3_FLAGS_ARCH(ptl2, i, x)
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#define SET_PTL3_FLAGS_ARCH(ptl2, i, x)
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#define SET_FRAME_FLAGS_ARCH(ptl3, i, x)    set_pt_level1_flags((pte_level1_t *)(ptl3), (index_t)(i), (x))
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#define SET_FRAME_FLAGS_ARCH(ptl3, i, x)    set_pt_level1_flags((pte_level1_t *)(ptl3), (index_t)(i), (x))
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#define PTE_VALID_ARCH(pte)                 (*((uint32_t *) (pte)) != 0)
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#define PTE_VALID_ARCH(pte)             (*((uint32_t *) (pte)) != 0)
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#define PTE_PRESENT_ARCH(pte)               ( ((pte_level0_t *)(pte))->descriptor_type != 0 )
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#define PTE_PRESENT_ARCH(pte)           ( ((pte_level0_t *)(pte))->descriptor_type != 0 )
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 97 
 
98 
/* pte should point into ptl3 */
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/* pte should point into ptl3 */
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#define PTE_GET_FRAME_ARCH(pte)             ( ((pte_level1_t *)(pte))->frame_base_addr << FRAME_WIDTH)
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#define PTE_GET_FRAME_ARCH(pte)         ( ((pte_level1_t *)(pte))->frame_base_addr << FRAME_WIDTH)
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/* pte should point into ptl3 */
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/* pte should point into ptl3 */
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#define PTE_WRITABLE_ARCH(pte)              ( ((pte_level1_t *)(pte))->access_permission_0 == PTE_AP_USER_RW_KERNEL_RW )
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#define PTE_WRITABLE_ARCH(pte)          ( ((pte_level1_t *)(pte))->access_permission_0 == PTE_AP_USER_RW_KERNEL_RW )
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 - 
 
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#define PTE_EXECUTABLE_ARCH(pte)            1
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#define PTE_EXECUTABLE_ARCH(pte)        1
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#ifndef __ASM__
 104 
#ifndef __ASM__
106 
 
 105 
 
- 
 
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/** Level 0 page table entry. */
- 
 
 107 
typedef struct {
- 
 
 108 
    /* 01b for coarse tables, see below for details */
- 
 
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    unsigned descriptor_type     : 2;
- 
 
 110 
    unsigned impl_specific       : 3;
- 
 
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    unsigned domain              : 4;
- 
 
 112 
    unsigned should_be_zero      : 1;
- 
 
 113 
    /* Pointer to the coarse 2nd level page table (holding entries for small (4KB)
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     * or large (64KB) pages. ARM also supports fine 2nd level page tables that
- 
 
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     * may hold even tiny pages (1KB) but they are bigger (4KB per table in comparison
- 
 
 116 
     * with 1KB per the coarse table)
- 
 
 117 
    */
- 
 
 118 
    unsigned coarse_table_addr   : 22;
- 
 
 119 
} __attribute__ ((packed)) pte_level0_t;
- 
 
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- 
 
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/** Level 1 page table entry (small (4KB) pages used) */
- 
 
 122 
typedef struct {
- 
 
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    /* 0b10 for small pages */
- 
 
 124 
    unsigned descriptor_type     : 2;
- 
 
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    unsigned bufferable          : 1;
- 
 
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    unsigned cacheable           : 1;
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    /* access permissions for each of 4 subparts of a page
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     * (for each 1KB when small pages used */
- 
 
 129 
    unsigned access_permission_0 : 2;
- 
 
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    unsigned access_permission_1 : 2;
- 
 
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    unsigned access_permission_2 : 2;
- 
 
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    unsigned access_permission_3 : 2;
- 
 
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    unsigned frame_base_addr     : 20;
- 
 
 134 
} __attribute__ ((packed)) pte_level1_t;
- 
 
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- 
 
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- 
 
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/* Level 1 page tables access permissions */
- 
 
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- 
 
 139 
/** User mode: no access, privileged mode: no access */
- 
 
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#define PTE_AP_USER_NO_KERNEL_NO 0
- 
 
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/** User mode: no access, privileged mode: read/write */
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#define PTE_AP_USER_NO_KERNEL_RW 1
- 
 
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/** User mode: read only, privileged mode: read/write */
- 
 
 144 
#define PTE_AP_USER_RO_KERNEL_RW 2
- 
 
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/** User mode: read/write, privileged mode: read/write */
- 
 
 146 
#define PTE_AP_USER_RW_KERNEL_RW 3
- 
 
 147 
 
- 
 
 148 
 
- 
 
 149 
/* pte_level0_t and pte_level1_t descriptor_type flags */
- 
 
 150 
 
- 
 
 151 
/** pte_level0_t and pte_level1_t "not present" flag (used in descriptor_type) */
- 
 
 152 
#define PTE_DESCRIPTOR_NOT_PRESENT  0
- 
 
 153 
/** pte_level0_t coarse page table flag (used in descriptor_type) */
- 
 
 154 
#define PTE_DESCRIPTOR_COARSE_TABLE 1
- 
 
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/** pte_level1_t small page table flag (used in descriptor type) */
- 
 
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#define PTE_DESCRIPTOR_SMALL_PAGE   2
- 
 
 157 
 
- 
 
 158 
 
107 
/**
 159 
/**
108 
 * Sets the address of level 0 page table.
 160 
 * Sets the address of level 0 page table.
109 
 *
 161 
 *
110 
 * \param pt    pointer to the page table to set
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 * \param pt    pointer to the page table to set
111 
 */  
 163 
 */  
112 
static inline void set_ptl0_addr( pte_level0_t* pt)
 164 
static inline void set_ptl0_addr( pte_level0_t* pt)
113 
{
 165 
{
- 
 
 166 
    asm volatile (
114 
    asm volatile ( "mcr p15, 0, %0, c2, c0, 0 \n"
 167 
        "mcr p15, 0, %0, c2, c0, 0 \n"
115 
        :
 168 
        :
116 
        : "r"(pt)
 169 
        : "r"(pt)
117 
    );
 170 
    );
118 
   
 - 
 
119 
}
 171 
}
120 
 
 172 
 
121 
/** Returns level 0 page table entry flags.
 173 
/** Returns level 0 page table entry flags.
122 
 *
 174 
 *
123 
 *  \param pt     level 0 page table
 175 
 *  \param pt     level 0 page table