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| Rev 2411 | Rev 2417 | ||
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| Line 57... | Line 57... | ||
| 57 | #ifdef KERNEL |
57 | #ifdef KERNEL |
| 58 | 58 | ||
| 59 | #define PTL0_ENTRIES_ARCH (2<<12) // 4096 |
59 | #define PTL0_ENTRIES_ARCH (2<<12) // 4096 |
| 60 | #define PTL1_ENTRIES_ARCH 0 |
60 | #define PTL1_ENTRIES_ARCH 0 |
| 61 | #define PTL2_ENTRIES_ARCH 0 |
61 | #define PTL2_ENTRIES_ARCH 0 |
| - | 62 | ||
| 62 | /* coarse page tables used (256*4 = 1KB per page) */ |
63 | /* coarse page tables used (256*4 = 1KB per page) */ |
| 63 | #define PTL3_ENTRIES_ARCH (2<<8) // 256 |
64 | #define PTL3_ENTRIES_ARCH (2<<8) // 256 |
| 64 | 65 | ||
| 65 | #define PTL0_SIZE_ARCH FOUR_FRAMES |
66 | #define PTL0_SIZE_ARCH FOUR_FRAMES |
| 66 | #define PTL1_SIZE_ARCH 0 |
67 | #define PTL1_SIZE_ARCH 0 |
| Line 96... | Line 97... | ||
| 96 | #define PTE_VALID_ARCH(pte) (*((uint32_t *) (pte)) != 0) |
97 | #define PTE_VALID_ARCH(pte) (*((uint32_t *) (pte)) != 0) |
| 97 | #define PTE_PRESENT_ARCH(pte) ( ((pte_level0_t *)(pte))->descriptor_type != 0 ) |
98 | #define PTE_PRESENT_ARCH(pte) ( ((pte_level0_t *)(pte))->descriptor_type != 0 ) |
| 98 | 99 | ||
| 99 | /* pte should point into ptl3 */ |
100 | /* pte should point into ptl3 */ |
| 100 | #define PTE_GET_FRAME_ARCH(pte) ( ((pte_level1_t *)(pte))->frame_base_addr << FRAME_WIDTH) |
101 | #define PTE_GET_FRAME_ARCH(pte) ( ((pte_level1_t *)(pte))->frame_base_addr << FRAME_WIDTH) |
| - | 102 | ||
| 101 | /* pte should point into ptl3 */ |
103 | /* pte should point into ptl3 */ |
| 102 | #define PTE_WRITABLE_ARCH(pte) ( ((pte_level1_t *)(pte))->access_permission_0 == PTE_AP_USER_RW_KERNEL_RW ) |
104 | #define PTE_WRITABLE_ARCH(pte) ( ((pte_level1_t *)(pte))->access_permission_0 == PTE_AP_USER_RW_KERNEL_RW ) |
| - | 105 | ||
| 103 | #define PTE_EXECUTABLE_ARCH(pte) 1 |
106 | #define PTE_EXECUTABLE_ARCH(pte) 1 |
| 104 | 107 | ||
| 105 | 108 | ||
| 106 | #ifndef __ASM__ |
109 | #ifndef __ASM__ |
| 107 | 110 | ||
| Line 118... | Line 121... | ||
| 118 | * or large (64KB) pages. ARM also supports fine 2nd level page tables that |
121 | * or large (64KB) pages. ARM also supports fine 2nd level page tables that |
| 119 | * may hold even tiny pages (1KB) but they are bigger (4KB per table in comparison |
122 | * may hold even tiny pages (1KB) but they are bigger (4KB per table in comparison |
| 120 | * with 1KB per the coarse table) |
123 | * with 1KB per the coarse table) |
| 121 | */ |
124 | */ |
| 122 | unsigned coarse_table_addr : 22; |
125 | unsigned coarse_table_addr : 22; |
| 123 | } __attribute__ ((packed)) pte_level0_t; |
126 | } ATTRIBUTE_PACKED pte_level0_t; |
| 124 | 127 | ||
| 125 | 128 | ||
| 126 | /** Level 1 page table entry (small (4KB) pages used). */ |
129 | /** Level 1 page table entry (small (4KB) pages used). */ |
| 127 | typedef struct { |
130 | typedef struct { |
| 128 | 131 | ||
| Line 136... | Line 139... | ||
| 136 | unsigned access_permission_0 : 2; |
139 | unsigned access_permission_0 : 2; |
| 137 | unsigned access_permission_1 : 2; |
140 | unsigned access_permission_1 : 2; |
| 138 | unsigned access_permission_2 : 2; |
141 | unsigned access_permission_2 : 2; |
| 139 | unsigned access_permission_3 : 2; |
142 | unsigned access_permission_3 : 2; |
| 140 | unsigned frame_base_addr : 20; |
143 | unsigned frame_base_addr : 20; |
| 141 | } __attribute__ ((packed)) pte_level1_t; |
144 | } ATTRIBUTE_PACKED pte_level1_t; |
| 142 | 145 | ||
| 143 | 146 | ||
| 144 | /* Level 1 page tables access permissions */ |
147 | /* Level 1 page tables access permissions */ |
| 145 | 148 | ||
| 146 | /** User mode: no access, privileged mode: no access. */ |
149 | /** User mode: no access, privileged mode: no access. */ |