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Line 53... Line 53...
53
#   define PA2KA(x) ((x) + 0x80000000)
53
#   define PA2KA(x) ((x) + 0x80000000)
54
#endif
54
#endif
55
 
55
 
56
#ifdef KERNEL
56
#ifdef KERNEL
57
 
57
 
58
// "small" pages (4KB) used
-
 
59
#define PTL0_ENTRIES_ARCH    (2<<12)    // 4096
58
#define PTL0_ENTRIES_ARCH    (2<<12)    // 4096
60
#define PTL1_ENTRIES_ARCH     0 
59
#define PTL1_ENTRIES_ARCH     0 
61
#define PTL2_ENTRIES_ARCH     0 
60
#define PTL2_ENTRIES_ARCH     0 
-
 
61
/* coarse page tables used (256*4 = 1KB per page) */
62
#define PTL3_ENTRIES_ARCH    (2<<8)     // 256
62
#define PTL3_ENTRIES_ARCH    (2<<8)     // 256
63
 
63
 
64
#define PTL0_INDEX_ARCH(vaddr)    (((vaddr) >> 20) & 0xfff)
64
#define PTL0_INDEX_ARCH(vaddr)    (((vaddr) >> 20) & 0xfff)
65
#define PTL1_INDEX_ARCH(vaddr)    0 
65
#define PTL1_INDEX_ARCH(vaddr)    0 
66
#define PTL2_INDEX_ARCH(vaddr)    0 
66
#define PTL2_INDEX_ARCH(vaddr)    0
-
 
67
/* TODO: ?? 0xfff or 0x0ff */
67
#define PTL3_INDEX_ARCH(vaddr)    (((vaddr) >> 12) & 0x0ff)
68
#define PTL3_INDEX_ARCH(vaddr)    (((vaddr) >> 12) & 0xfff)
68
 
69
 
69
#define GET_PTL1_ADDRESS_ARCH(ptl0, i)      ((pte_t *)( (((pte_level0_t*)(ptl0))[(i)]).coarse_table_addr << 10 ))
70
#define GET_PTL1_ADDRESS_ARCH(ptl0, i)      ((pte_t *)( (((pte_level0_t*)(ptl0))[(i)]).coarse_table_addr << 10 ))
70
#define GET_PTL2_ADDRESS_ARCH(ptl1, i)      (ptl1)
71
#define GET_PTL2_ADDRESS_ARCH(ptl1, i)      (ptl1)
71
#define GET_PTL3_ADDRESS_ARCH(ptl2, i)      (ptl2)
72
#define GET_PTL3_ADDRESS_ARCH(ptl2, i)      (ptl2)
72
#define GET_FRAME_ADDRESS_ARCH(ptl3, i)     ((uintptr_t)( (((pte_level1_t*)(ptl3))[(i)]).frame_base_addr << 12 ))
73
#define GET_FRAME_ADDRESS_ARCH(ptl3, i)     ((uintptr_t)( (((pte_level1_t*)(ptl3))[(i)]).frame_base_addr << 12 ))
Line 86... Line 87...
86
#define SET_PTL2_FLAGS_ARCH(ptl1, i, x)
87
#define SET_PTL2_FLAGS_ARCH(ptl1, i, x)
87
#define SET_PTL3_FLAGS_ARCH(ptl2, i, x)
88
#define SET_PTL3_FLAGS_ARCH(ptl2, i, x)
88
#define SET_FRAME_FLAGS_ARCH(ptl3, i, x)    set_pt_level1_flags((pte_level1_t *)(ptl3), (index_t)(i), (x))
89
#define SET_FRAME_FLAGS_ARCH(ptl3, i, x)    set_pt_level1_flags((pte_level1_t *)(ptl3), (index_t)(i), (x))
89
 
90
 
90
#define PTE_VALID_ARCH(pte)                 (*((uint32_t *) (pte)) != 0)
91
#define PTE_VALID_ARCH(pte)                 (*((uint32_t *) (pte)) != 0)
-
 
92
// TODO: ?? != 0
91
#define PTE_PRESENT_ARCH(pte)               ( ((pte_level0_t *)(pte))->descriptor_type )
93
#define PTE_PRESENT_ARCH(pte)               ( ((pte_level0_t *)(pte))->descriptor_type != 0 )
-
 
94
 
92
// pte should point into ptl3 
95
/* pte should point into ptl3 */
93
#define PTE_GET_FRAME_ARCH(pte)             ( ((pte_level1_t *)(pte))->frame_base_addr << FRAME_WIDTH)
96
#define PTE_GET_FRAME_ARCH(pte)             ( ((pte_level1_t *)(pte))->frame_base_addr << FRAME_WIDTH)
94
// pte should point into ptl3 
97
/* pte should point into ptl3 */
95
#define PTE_WRITABLE_ARCH(pte)              ( ((pte_level1_t *)(pte))->access_permission_0 == pte_ap_user_rw_kernel_rw ) 
98
#define PTE_WRITABLE_ARCH(pte)              ( ((pte_level1_t *)(pte))->access_permission_0 == pte_ap_user_rw_kernel_rw ) 
-
 
99
 
96
#define PTE_EXECUTABLE_ARCH(pte)            1
100
#define PTE_EXECUTABLE_ARCH(pte)            1
97
 
101
 
98
#ifndef __ASM__
102
#ifndef __ASM__
99
 
103
 
-
 
104
/**
100
/** Sets the address of level 0 page table.
105
 * Sets the address of level 0 page table.
-
 
106
 *
101
 * \param pt pointer to the page table to set
107
 * \param pt    pointer to the page table to set
102
 */  
108
 */  
103
static inline void set_ptl0_addr( pte_level0_t* pt)
109
static inline void set_ptl0_addr( pte_level0_t* pt)
104
{
110
{
105
    asm volatile ( "mcr p15, 0, %0, c2, c0, 0 \n"
111
    asm volatile ( "mcr p15, 0, %0, c2, c0, 0 \n"
106
        :
112
        :
107
        : "r"(pt)
113
        : "r"(pt)
108
    );
114
    );
109
   
115
   
110
}
116
}
111
 
117
 
-
 
118
/**
-
 
119
 * Returns level 0 page table entry flags.
-
 
120
 *
-
 
121
 * \param pt     level 0 page table
112
//TODO Comment: Page table structure as in other architectures
122
 * \param i      index of the entry to return
-
 
123
 */
113
static inline int get_pt_level0_flags(pte_level0_t *pt, index_t i)
124
static inline int get_pt_level0_flags(pte_level0_t *pt, index_t i)
114
{
125
{
115
    pte_level0_t *p = &pt[i];
126
    pte_level0_t *p = &pt[i];
116
 
127
 
117
    return (
128
    return (
118
        ( p->descriptor_type != pte_descriptor_not_preset ) << PAGE_PRESENT_SHIFT |
129
        ( p->descriptor_type != pte_descriptor_not_preset ) << PAGE_PRESENT_SHIFT |
-
 
130
        ( 1 << PAGE_USER_SHIFT )  |
119
        ( 1 << PAGE_READ_SHIFT ) |
131
        ( 1 << PAGE_READ_SHIFT )  |
-
 
132
        ( 1 << PAGE_WRITE_SHIFT ) |
120
        ( 1 << PAGE_EXEC_SHIFT ) |
133
        ( 1 << PAGE_EXEC_SHIFT )  |
121
        ( 1 << PAGE_CACHEABLE  )
134
        ( 1 << PAGE_CACHEABLE_SHIFT  )
122
    );
135
    );
123
}
136
}
124
 
137
 
-
 
138
/**
-
 
139
 * Returns level 1 page table entry flags.
-
 
140
 *
-
 
141
 * \param pt     level 1 page table
-
 
142
 * \param i      index of the entry to return
-
 
143
 */
125
static inline int get_pt_level1_flags(pte_level1_t *pt, index_t i)
144
static inline int get_pt_level1_flags(pte_level1_t *pt, index_t i)
126
{
145
{
127
  pte_level1_t *p = &pt[i];
146
    pte_level1_t *p = &pt[i];
128
 
147
 
129
    return (
148
    return (
130
        ( p->descriptor_type != pte_descriptor_not_preset )    << PAGE_PRESENT_SHIFT |
149
        ( p->descriptor_type != pte_descriptor_not_preset )    << PAGE_PRESENT_SHIFT |
131
        ( (p->access_permission_0 == pte_ap_user_ro_kernel_rw) << PAGE_READ_SHIFT )  |
150
        ( (p->access_permission_0 == pte_ap_user_ro_kernel_rw) << PAGE_READ_SHIFT )  |
132
        ( (p->access_permission_0 == pte_ap_user_rw_kernel_rw) << PAGE_READ_SHIFT )  |
151
        ( (p->access_permission_0 == pte_ap_user_rw_kernel_rw) << PAGE_READ_SHIFT )  |
133
        ( (p->access_permission_0 == pte_ap_user_rw_kernel_rw) << PAGE_WRITE_SHIFT ) |
152
        ( (p->access_permission_0 == pte_ap_user_rw_kernel_rw) << PAGE_WRITE_SHIFT ) |
134
        ( (p->access_permission_0 != pte_ap_user_no_kernel_rw) << PAGE_USER_SHIFT )  |
153
        ( (p->access_permission_0 != pte_ap_user_no_kernel_rw) << PAGE_USER_SHIFT )  |
135
        ( 1 << PAGE_EXEC_SHIFT ) |
154
        ( 1 << PAGE_EXEC_SHIFT ) |
136
        ( p->bufferable << PAGE_CACHEABLE  )
155
        ( p->bufferable << PAGE_CACHEABLE )
137
 
-
 
138
 
-
 
139
    );
156
    );
140
 
-
 
141
}
157
}
142
 
158
 
-
 
159
/**
-
 
160
 * Sets flags of level 0 page table entry.
-
 
161
 *
-
 
162
 * \param pt     level 0 page table
-
 
163
 * \param i      index of the entry to be changed
-
 
164
 * \param flags  new flags
-
 
165
 *
-
 
166
 * TODO: why should_be_zero set to 1?
-
 
167
 */
143
static inline void set_pt_level0_flags(pte_level0_t *pt, index_t i, int flags)
168
static inline void set_pt_level0_flags(pte_level0_t *pt, index_t i, int flags)
144
{
169
{
145
    pte_level0_t *p = &pt[i];
170
    pte_level0_t *p = &pt[i];
146
   
171
   
147
    if ( flags & PAGE_NOT_PRESENT ) {
172
    if (flags & PAGE_NOT_PRESENT) {
148
        p->descriptor_type = pte_descriptor_not_preset;
173
        p->descriptor_type = pte_descriptor_not_preset;
149
        p->should_be_zero  = 1;
174
        p->should_be_zero  = 1;
150
    } else {
175
    } else {
151
        p->descriptor_type = pte_descriptor_coarse_table;
176
        p->descriptor_type = pte_descriptor_coarse_table;
152
        p->should_be_zero  = 0;
177
        p->should_be_zero  = 0;
153
    }
178
    }
154
}
179
}
155
 
180
 
-
 
181
/**
-
 
182
 * Sets flags of level 1 page table entry.
-
 
183
 *
156
/* TODO: rewrite comment: We use same acess rights for whole page, so if page is set as not preset then
184
 * We use same access rights for the whole page. When page is not preset then
157
 * in acess_rigts_3 set value 1
185
 * store 1 in acess_rigts_3.
-
 
186
 * TODO: why access_right_3?
-
 
187
 *
-
 
188
 * \param pt     level 1 page table
-
 
189
 * \param i      index of the entry to be changed
-
 
190
 * \param flags  new flags
158
 */  
191
 */  
159
static inline void set_pt_level1_flags(pte_level1_t *pt, index_t i, int flags)
192
static inline void set_pt_level1_flags(pte_level1_t *pt, index_t i, int flags)
160
{
193
{
161
    pte_level1_t *p = &pt[i];
194
    pte_level1_t *p = &pt[i];
162
   
195
   
163
    if ( flags & PAGE_NOT_PRESENT ) {
196
    if (flags & PAGE_NOT_PRESENT) {
164
        p->descriptor_type      = pte_descriptor_not_preset;
197
        p->descriptor_type      = pte_descriptor_not_preset;
165
        p->access_permission_3  = 1;
198
        p->access_permission_3  = 1;
166
    } else {
199
    } else {
167
        p->descriptor_type      = pte_descriptor_coarse_table;
200
        p->descriptor_type      = pte_descriptor_small_page;
168
        p->access_permission_3  = p->access_permission_0;
201
        p->access_permission_3  = p->access_permission_0;
169
    }
202
    }
170
 
203
 
171
    p->cacheable = p->bufferable = (flags & PAGE_CACHEABLE) != 0;
204
    p->cacheable = p->bufferable = (flags & PAGE_CACHEABLE) != 0;
172
 
205
 
173
    // default kernel rw, user none
206
    /* default access permission */
174
    p->access_permission_0 = p->access_permission_1 =
207
    p->access_permission_0 = p->access_permission_1 =
175
        p->access_permission_2 = p->access_permission_3 = pte_ap_user_no_kernel_rw;
208
        p->access_permission_2 = p->access_permission_3 = pte_ap_user_no_kernel_rw;
176
 
209
 
177
    if ( flags & PAGE_USER )  {
210
    if (flags & PAGE_USER)  {
178
        if ( flags & PAGE_READ ) {
211
        if (flags & PAGE_READ) {
179
            p->access_permission_0 = p->access_permission_1 =
212
            p->access_permission_0 = p->access_permission_1 =
180
                p->access_permission_2 = p->access_permission_3 =
213
                p->access_permission_2 = p->access_permission_3 =
181
                pte_ap_user_ro_kernel_rw;
214
                pte_ap_user_ro_kernel_rw;
182
        }
215
        }
183
        if ( flags & PAGE_WRITE ) {
216
        if (flags & PAGE_WRITE) {
184
            p->access_permission_0 = p->access_permission_1 =
217
            p->access_permission_0 = p->access_permission_1 =
185
                p->access_permission_2 = p->access_permission_3 =
218
                p->access_permission_2 = p->access_permission_3 =
186
                pte_ap_user_rw_kernel_rw;
219
                pte_ap_user_rw_kernel_rw;
187
        }
220
        }
188
    }
221
    }