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| Rev 2147 | Rev 2149 | ||
|---|---|---|---|
| Line 61... | Line 61... | ||
| 61 | #define PTL1_INDEX_ARCH(vaddr) 0 |
61 | #define PTL1_INDEX_ARCH(vaddr) 0 |
| 62 | #define PTL2_INDEX_ARCH(vaddr) 0 |
62 | #define PTL2_INDEX_ARCH(vaddr) 0 |
| 63 | #define PTL3_INDEX_ARCH(vaddr) (((vaddr) >> 12) & 0x0ff) |
63 | #define PTL3_INDEX_ARCH(vaddr) (((vaddr) >> 12) & 0x0ff) |
| 64 | 64 | ||
| 65 | 65 | ||
| 66 | #define GET_PTL1_ADDRESS_ARCH(ptl0, i) ((pte_t *)( (((pte_level0_t*)(ptl0))[(i)]) & 0xfffffc00 ) |
66 | #define GET_PTL1_ADDRESS_ARCH(ptl0, i) ((pte_t *)( (((pte_level0_t*)(ptl0))[(i)]).coarse_table_addr << 10 )) |
| 67 | #define GET_PTL2_ADDRESS_ARCH(ptl1, i) (ptl1) |
67 | #define GET_PTL2_ADDRESS_ARCH(ptl1, i) (ptl1) |
| 68 | #define GET_PTL3_ADDRESS_ARCH(ptl2, i) (ptl2) |
68 | #define GET_PTL3_ADDRESS_ARCH(ptl2, i) (ptl2) |
| 69 | #define GET_FRAME_ADDRESS_ARCH(ptl3, i) ( (uintptr_t)(((pte_level1_t*)(ptl3))[(i)]) & 0xfffff000 ) |
69 | #define GET_FRAME_ADDRESS_ARCH(ptl3, i) ( (uintptr_t)(((pte_level1_t*)(ptl3))[(i)]).frame_base_addr << 12 )) |
| 70 | 70 | ||
| 71 | #define SET_PTL0_ADDRESS_ARCH(ptl0) // TODO |
71 | #define SET_PTL0_ADDRESS_ARCH(ptl0) // TODO |
| 72 | #define SET_PTL1_ADDRESS_ARCH(ptl0, i, a) (((pte_level0_t *)(ptl0))[(i)].coarse_table_addr = (a)>>10) |
72 | #define SET_PTL1_ADDRESS_ARCH(ptl0, i, a) (((pte_level0_t *)(ptl0))[(i)].coarse_table_addr = (a)>>10) |
| 73 | #define SET_PTL2_ADDRESS_ARCH(ptl1, i, a) |
73 | #define SET_PTL2_ADDRESS_ARCH(ptl1, i, a) |
| 74 | #define SET_PTL3_ADDRESS_ARCH(ptl2, i, a) |
74 | #define SET_PTL3_ADDRESS_ARCH(ptl2, i, a) |
| Line 80... | Line 80... | ||
| 80 | #define GET_FRAME_FLAGS_ARCH(ptl3, i) get_pt_level1_flags((pte_level1_t *)(ptl3), (index_t)(i)) |
80 | #define GET_FRAME_FLAGS_ARCH(ptl3, i) get_pt_level1_flags((pte_level1_t *)(ptl3), (index_t)(i)) |
| 81 | 81 | ||
| 82 | #define SET_PTL1_FLAGS_ARCH(ptl0, i, x) set_pt_level0_flags((pte_level0_t *)(ptl0), (index_t)(i), (x)) |
82 | #define SET_PTL1_FLAGS_ARCH(ptl0, i, x) set_pt_level0_flags((pte_level0_t *)(ptl0), (index_t)(i), (x)) |
| 83 | #define SET_PTL2_FLAGS_ARCH(ptl1, i, x) |
83 | #define SET_PTL2_FLAGS_ARCH(ptl1, i, x) |
| 84 | #define SET_PTL3_FLAGS_ARCH(ptl2, i, x) |
84 | #define SET_PTL3_FLAGS_ARCH(ptl2, i, x) |
| 85 | #define SET_FRAME_FLAGS_ARCH(ptl3, i, x) set_pt_level1_flags((pte_level1t *)(ptl3), (index_t)(i), (x)) |
85 | #define SET_FRAME_FLAGS_ARCH(ptl3, i, x) set_pt_level1_flags((pte_level1_t *)(ptl3), (index_t)(i), (x)) |
| 86 | 86 | ||
| 87 | #define PTE_VALID_ARCH(pte) (*((uint32_t *) (pte)) != 0) |
87 | #define PTE_VALID_ARCH(pte) (*((uint32_t *) (pte)) != 0) |
| 88 | #define PTE_PRESENT_ARCH(pte) ( ((pte_level0_t *)(pte))->descriptor_type ) |
88 | #define PTE_PRESENT_ARCH(pte) ( ((pte_level0_t *)(pte))->descriptor_type ) |
| 89 | #define PTE_GET_FRAME_ARCH(pte) ( ((pte_level1_t *)(pte))->frame_base_addr << FRAME_WIDTH) // pte should point into ptl3 |
89 | #define PTE_GET_FRAME_ARCH(pte) ( ((pte_level1_t *)(pte))->frame_base_addr << FRAME_WIDTH) // pte should point into ptl3 |
| 90 | #define PTE_WRITABLE_ARCH(pte) ( ((pte_level1_t *)(pte))->access_permission_0 == pte_ap_user_rw_kernel_rw ) // pte should point into ptl3 |
90 | #define PTE_WRITABLE_ARCH(pte) ( ((pte_level1_t *)(pte))->access_permission_0 == pte_ap_user_rw_kernel_rw ) // pte should point into ptl3 |
| Line 100... | Line 100... | ||
| 100 | static inline int get_pt_level0_flags(pte_level0_t *pt, index_t i) |
100 | static inline int get_pt_level0_flags(pte_level0_t *pt, index_t i) |
| 101 | { |
101 | { |
| 102 | pte_level0_t *p = &pt[i]; |
102 | pte_level0_t *p = &pt[i]; |
| 103 | 103 | ||
| 104 | return ( |
104 | return ( |
| 105 | ( p->destriptor_type != pte_descriptor_not_preset ) << PAGE_PRESENT_SHIFT | |
105 | ( p->descriptor_type != pte_descriptor_not_preset ) << PAGE_PRESENT_SHIFT | |
| 106 | ( 1 << PAGE_READ_SHIFT ) | |
106 | ( 1 << PAGE_READ_SHIFT ) | |
| 107 | ( 1 << PAGE_EXEC_SHIFT ) | |
107 | ( 1 << PAGE_EXEC_SHIFT ) | |
| 108 | ( 1 << PAGE_CACHEABLE ) |
108 | ( 1 << PAGE_CACHEABLE ) |
| 109 | // Alf Note: MayBe return WriteAble because level0 should use only kernel which can write |
109 | // Alf Note: MayBe return WriteAble because level0 should use only kernel which can write |
| 110 | // Alf Note: MayBe return global flag if index i > 2048 (horni 2GB because kernel is mapped globaly) |
110 | // Alf Note: MayBe return global flag if index i > 2048 (horni 2GB because kernel is mapped globaly) |
| 111 | ); |
111 | ); |
| 112 | 112 | ||
| 113 | } |
113 | } |
| 114 | static inline int get_pt_level1_flags(pte_t *pt, index_t i) |
114 | static inline int get_pt_level1_flags(pte_level1_t *pt, index_t i) |
| 115 | { |
115 | { |
| 116 | pte_level1_t *p = &pt[i]; |
116 | pte_level1_t *p = &pt[i]; |
| 117 | 117 | ||
| 118 | return ( |
118 | return ( |
| 119 | ( p->destriptor_type != pte_descriptor_not_preset ) << PAGE_PRESENT_SHIFT | |
119 | ( p->descriptor_type != pte_descriptor_not_preset ) << PAGE_PRESENT_SHIFT | |
| 120 | ( (p->access_permission_0 == pte_ap_user_ro_kernel_rw) << PAGE_READ_SHIFT ) | |
120 | ( (p->access_permission_0 == pte_ap_user_ro_kernel_rw) << PAGE_READ_SHIFT ) | |
| 121 | ( (p->access_permission_0 == pte_ap_user_rw_kernel_rw) << PAGE_READ_SHIFT ) | |
121 | ( (p->access_permission_0 == pte_ap_user_rw_kernel_rw) << PAGE_READ_SHIFT ) | |
| 122 | ( (p->access_permission_0 == pte_ap_user_rw_kernel_rw) << PAGE_WRITE_SHIFT ) | |
122 | ( (p->access_permission_0 == pte_ap_user_rw_kernel_rw) << PAGE_WRITE_SHIFT ) | |
| 123 | ( (p->access_permission_0 != pte_ap_user_no_kernel_rw) << PAGE_USER_SHIFT ) | |
123 | ( (p->access_permission_0 != pte_ap_user_no_kernel_rw) << PAGE_USER_SHIFT ) | |
| 124 | ( 1 << PAGE_EXEC_SHIFT ) | |
124 | ( 1 << PAGE_EXEC_SHIFT ) | |
| Line 134... | Line 134... | ||
| 134 | static inline void set_pt_level0_flags(pte_level0_t *pt, index_t i, int flags) |
134 | static inline void set_pt_level0_flags(pte_level0_t *pt, index_t i, int flags) |
| 135 | { |
135 | { |
| 136 | pte_level0_t *p = &pt[i]; |
136 | pte_level0_t *p = &pt[i]; |
| 137 | 137 | ||
| 138 | if ( flags & PAGE_NOT_PRESENT ) { |
138 | if ( flags & PAGE_NOT_PRESENT ) { |
| 139 | p->destriptor_type = pte_descriptor_not_preset; |
139 | p->descriptor_type = pte_descriptor_not_preset; |
| 140 | p->should_be_zero = 1; |
140 | p->should_be_zero = 1; |
| 141 | } else |
141 | } else |
| 142 | { |
142 | { |
| 143 | p->destriptor_type = pte_descriptor_coarse_table; |
143 | p->descriptor_type = pte_descriptor_coarse_table; |
| 144 | p->should_be_zero = 0; |
144 | p->should_be_zero = 0; |
| 145 | } |
145 | } |
| 146 | return; |
146 | return; |
| 147 | } |
147 | } |
| 148 | 148 | ||
| Line 152... | Line 152... | ||
| 152 | static inline void set_pt_level1_flags(pte_level1_t *pt, index_t i, int flags) |
152 | static inline void set_pt_level1_flags(pte_level1_t *pt, index_t i, int flags) |
| 153 | { |
153 | { |
| 154 | pte_level1_t *p = &pt[i]; |
154 | pte_level1_t *p = &pt[i]; |
| 155 | 155 | ||
| 156 | if ( flags & PAGE_NOT_PRESENT ) { |
156 | if ( flags & PAGE_NOT_PRESENT ) { |
| 157 | p->destriptor_type = pte_descriptor_not_preset; |
157 | p->descriptor_type = pte_descriptor_not_preset; |
| 158 | p->access_permission_3 = 1; // Ensure not all bits set to zero ... correct acess rights are stored in other 0-2 access permission entries |
158 | p->access_permission_3 = 1; // Ensure not all bits set to zero ... correct acess rights are stored in other 0-2 access permission entries |
| 159 | } else |
159 | } else |
| 160 | { |
160 | { |
| 161 | p->destriptor_type = pte_descriptor_coarse_table; |
161 | p->descriptor_type = pte_descriptor_coarse_table; |
| 162 | p->access_permission_3 = p->access_permission_0; |
162 | p->access_permission_3 = p->access_permission_0; |
| 163 | } |
163 | } |
| 164 | 164 | ||
| 165 | p->cacheable = p->bufferable = (flags & PAGE_CACHEABLE) != 0; |
165 | p->cacheable = p->bufferable = (flags & PAGE_CACHEABLE) != 0; |
| 166 | // default kernel rw, user none |
166 | // default kernel rw, user none |