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| 24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
| 25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
| 26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| 27 | */ |
27 | */ |
| 28 | 28 | ||
| - | 29 | ||
| 29 | /** @addtogroup arm32boot |
30 | /** @addtogroup arm32boot |
| 30 | * @{ |
31 | * @{ |
| 31 | */ |
32 | */ |
| 32 | /** @file |
33 | /** @file |
| 33 | */ |
34 | */ |
| 34 | 35 | ||
| 35 | 36 | ||
| 36 | #ifndef __MM_H__ |
37 | #ifndef BOOT_arm32__MM_H |
| 37 | #define __MM_H__ |
38 | #define BOOT_arm32__MM_H |
| - | 39 | ||
| 38 | 40 | ||
| 39 | #ifndef __ASM__ |
41 | #ifndef __ASM__ |
| 40 | #include "types.h" |
42 | #include "types.h" |
| 41 | #endif |
43 | #endif |
| 42 | 44 | ||
| 43 | 45 | ||
| - | 46 | /** Frame width. */ |
|
| 44 | #define FRAME_WIDTH 12 /* 4KB frames */ |
47 | #define FRAME_WIDTH 12 /* 4KB frames */ |
| - | 48 | ||
| - | 49 | /** Frame size. */ |
|
| 45 | #define FRAME_SIZE (1 << FRAME_WIDTH) |
50 | #define FRAME_SIZE (1 << FRAME_WIDTH) |
| - | 51 | ||
| - | 52 | /** Page size in 2-level paging which is switched on later in the kernel initialization. */ |
|
| - | 53 | #define PAGE_SIZE FRAME_SIZE |
|
| 46 | 54 | ||
| 47 | #define PAGE_WIDTH FRAME_WIDTH |
- | |
| 48 | #define PAGE_SIZE FRAME_SIZE |
- | |
| 49 | 55 | ||
| 50 | #ifndef __ASM__ |
56 | #ifndef __ASM__ |
| 51 | # define KA2PA(x) (((uintptr_t) (x)) - 0x80000000) |
57 | # define KA2PA(x) (((uintptr_t) (x)) - 0x80000000) |
| 52 | # define PA2KA(x) (((uintptr_t) (x)) + 0x80000000) |
58 | # define PA2KA(x) (((uintptr_t) (x)) + 0x80000000) |
| 53 | #else |
59 | #else |
| 54 | # define KA2PA(x) ((x) - 0x80000000) |
60 | # define KA2PA(x) ((x) - 0x80000000) |
| 55 | # define PA2KA(x) ((x) + 0x80000000) |
61 | # define PA2KA(x) ((x) + 0x80000000) |
| 56 | #endif |
62 | #endif |
| 57 | 63 | ||
| 58 | /** Number of entries in PTL0 */ |
- | |
| 59 | #define PTL0_ENTRIES_ARCH (1<<12) /* 4096 */ |
- | |
| 60 | 64 | ||
| - | 65 | /** Number of entries in PTL0. */ |
|
| - | 66 | #define PTL0_ENTRIES (1<<12) /* 4096 */ |
|
| - | 67 | ||
| - | 68 | /** Size of an entry in PTL0. */ |
|
| - | 69 | #define PTL0_ENTRY_SIZE 4 |
|
| - | 70 | ||
| 61 | /** Frames per 1MB section */ |
71 | /** Number of frames per 1MB section. */ |
| 62 | #define FRAMES_PER_SECTION ( ( 1 << 20 ) / FRAME_SIZE ) |
72 | #define FRAMES_PER_SECTION ( ( 1 << 20 ) / FRAME_SIZE ) |
| 63 | 73 | ||
| 64 | /** Converts adress to frame number */ |
74 | /** Returns number of frame the address belongs to. */ |
| 65 | #define ADDR2PFN( addr ) ( ((uintptr_t)(addr))>>FRAME_WIDTH ) |
75 | #define ADDR2PFN( addr ) ( ((uintptr_t)(addr)) >> FRAME_WIDTH ) |
| 66 | 76 | ||
| 67 | /** Descriptor type that signs "section" page table entry |
77 | /** Describes "section" page table entry (one-level paging with 1MB sized pages). */ |
| - | 78 | #define PTE_DESCRIPTOR_SECTION 0x2 |
|
| - | 79 | ||
| 68 | * (one-level paging with 1MB sized pages) */ |
80 | /** Page table access rights: user - no access, kernel - read/write. */ |
| 69 | #define PTE_DESCRIPTOR_SECTION 2 |
81 | #define PTE_AP_USER_NO_KERNEL_RW 0x1 |
| 70 | 82 | ||
| 71 | /** Access rights to page table: user-no access, kernel-read/write */ |
- | |
| 72 | #define PTE_AP_USER_NO_KERNEL_RW 1 |
- | |
| 73 | 83 | ||
| 74 | #ifndef __ASM__ |
84 | #ifndef __ASM__ |
| 75 | 85 | ||
| 76 | 86 | ||
| 77 | /** Page table level 0 entry - "section" format (one-level paging, 1MB sized |
87 | /** Page table level 0 entry - "section" format is used (one-level paging, 1MB sized |
| 78 | * pages). Used only for booting the kernel. */ |
88 | * pages). Used only while booting the kernel. */ |
| 79 | typedef struct { |
89 | typedef struct { |
| 80 | unsigned descriptor_type : 2; |
90 | unsigned descriptor_type : 2; |
| 81 | unsigned bufferable : 1; |
91 | unsigned bufferable : 1; |
| 82 | unsigned cacheable : 1; |
92 | unsigned cacheable : 1; |
| 83 | unsigned impl_specific : 1; |
93 | unsigned impl_specific : 1; |
| Line 87... | Line 97... | ||
| 87 | unsigned should_be_zero_2 : 8; |
97 | unsigned should_be_zero_2 : 8; |
| 88 | unsigned section_base_addr : 12; |
98 | unsigned section_base_addr : 12; |
| 89 | } __attribute__ ((packed)) pte_level0_section_t; |
99 | } __attribute__ ((packed)) pte_level0_section_t; |
| 90 | 100 | ||
| 91 | 101 | ||
| 92 | /** Page table that holds 1:1 mapping for booting the kernel. */ |
102 | /** Page table that holds 1:1 virtual to physical mapping used while booting the kernel. */ |
| 93 | extern pte_level0_section_t page_table[PTL0_ENTRIES_ARCH]; |
103 | extern pte_level0_section_t page_table[PTL0_ENTRIES]; |
| 94 | - | ||
| 95 | 104 | ||
| 96 | /** Starts the MMU - initializes page table and enables paging. */ |
- | |
| 97 | void mmu_start(void); |
105 | extern void mmu_start(void); |
| 98 | 106 | ||
| 99 | 107 | ||
| 100 | /** Enables paging. */ |
108 | /** Enables paging. */ |
| 101 | static inline void enable_paging() |
109 | static inline void enable_paging() |
| 102 | { |
110 | { |
| Line 105... | Line 113... | ||
| 105 | */ |
113 | */ |
| 106 | asm volatile ( |
114 | asm volatile ( |
| 107 | // behave as a client of domains |
115 | // behave as a client of domains |
| 108 | "ldr r0, =0x55555555 \n" |
116 | "ldr r0, =0x55555555 \n" |
| 109 | "mcr p15, 0, r0, c3, c0, 0 \n" |
117 | "mcr p15, 0, r0, c3, c0, 0 \n" |
| - | 118 | ||
| 110 | // current settings |
119 | // current settings |
| 111 | "mrc p15, 0, r0, c1, c0, 0 \n" |
120 | "mrc p15, 0, r0, c1, c0, 0 \n" |
| 112 | /* TODO: talk to Alf why needed |
- | |
| 113 | // mask to disable aligment checks; system & rom bit set to 0 (has no |
- | |
| 114 | // special effect) |
- | |
| 115 | "ldr r1, =0xfffffe8f \n" |
- | |
| 116 | "and r0, r0, r1 \n" |
- | |
| 117 | */ |
121 | |
| 118 | // mask to enable paging |
122 | // mask to enable paging |
| 119 | "ldr r1, =0x00000001 \n" |
123 | "ldr r1, =0x00000001 \n" |
| 120 | "orr r0, r0, r1 \n" |
124 | "orr r0, r0, r1 \n" |
| - | 125 | ||
| 121 | // store settings |
126 | // store settings |
| 122 | "mcr p15, 0, r0, c1, c0, 0 \n" |
127 | "mcr p15, 0, r0, c1, c0, 0 \n" |
| 123 | : |
128 | : |
| 124 | : |
129 | : |
| 125 | : "r0", "r1" |
130 | : "r0", "r1" |
| 126 | ); |
131 | ); |
| 127 | } |
132 | } |
| 128 | 133 | ||
| 129 | 134 | ||
| 130 | /** Sets the address of level 0 page table. |
135 | /** Sets the address of level 0 page table to CP15 register 2. |
| - | 136 | * |
|
| 131 | * \param pt pointer to the page table to set |
137 | * @param pt Address of a page table to set. |
| 132 | */ |
138 | */ |
| 133 | static inline void set_ptl0_address(pte_level0_section_t* pt) |
139 | static inline void set_ptl0_address(pte_level0_section_t* pt) |
| 134 | { |
140 | { |
| - | 141 | asm volatile ( |
|
| 135 | asm volatile ( "mcr p15, 0, %0, c2, c0, 0 \n" |
142 | "mcr p15, 0, %0, c2, c0, 0 \n" |
| 136 | : |
143 | : |
| 137 | : "r"(pt) |
144 | : "r"(pt) |
| 138 | ); |
145 | ); |
| 139 | } |
146 | } |
| 140 | 147 | ||
| - | 148 | ||
| 141 | #endif |
149 | #endif |
| 142 | 150 | ||
| 143 | #endif |
151 | #endif |
| 144 | 152 | ||
| 145 | /** @} |
153 | /** @} |