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| Rev 2254 | Rev 2257 | ||
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| 84 | unsigned domain : 4; |
84 | unsigned domain : 4; |
| 85 | unsigned should_be_zero_1 : 1; |
85 | unsigned should_be_zero_1 : 1; |
| 86 | unsigned access_permission : 2; |
86 | unsigned access_permission : 2; |
| 87 | unsigned should_be_zero_2 : 8; |
87 | unsigned should_be_zero_2 : 8; |
| 88 | unsigned section_base_addr : 12; |
88 | unsigned section_base_addr : 12; |
| 89 | } __attribute__ ((packed)) pte_level0_section; |
89 | } __attribute__ ((packed)) pte_level0_section_t; |
| 90 | 90 | ||
| 91 | 91 | ||
| 92 | /** Page table that holds 1:1 mapping for booting the kernel. */ |
92 | /** Page table that holds 1:1 mapping for booting the kernel. */ |
| 93 | extern pte_level0_section page_table[PTL0_ENTRIES_ARCH]; |
93 | extern pte_level0_section_t page_table[PTL0_ENTRIES_ARCH]; |
| 94 | 94 | ||
| 95 | 95 | ||
| 96 | /** Starts the MMU - initializes page table and enables paging. */ |
96 | /** Starts the MMU - initializes page table and enables paging. */ |
| 97 | void mmu_start(void); |
97 | void mmu_start(void); |
| 98 | 98 | ||
| Line 128... | Line 128... | ||
| 128 | 128 | ||
| 129 | 129 | ||
| 130 | /** Sets the address of level 0 page table. |
130 | /** Sets the address of level 0 page table. |
| 131 | * \param pt pointer to the page table to set |
131 | * \param pt pointer to the page table to set |
| 132 | */ |
132 | */ |
| 133 | static inline void set_ptl0_address(pte_level0_section* pt) |
133 | static inline void set_ptl0_address(pte_level0_section_t* pt) |
| 134 | { |
134 | { |
| 135 | asm volatile ( "mcr p15, 0, %0, c2, c0, 0 \n" |
135 | asm volatile ( "mcr p15, 0, %0, c2, c0, 0 \n" |
| 136 | : |
136 | : |
| 137 | : "r"(pt) |
137 | : "r"(pt) |
| 138 | ); |
138 | ); |
| 139 | } |
139 | } |
| 140 | 140 | ||
| 141 | #endif |
141 | #endif |