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/** Access rights to page table: user-no access, kernel-read/write */
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/** Access rights to page table: user-no access, kernel-read/write */
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#define PTE_AP_USER_NO_KERNEL_RW            1
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#define PTE_AP_USER_NO_KERNEL_RW            1
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#ifndef __ASM__
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#ifndef __ASM__
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/** Page table level 0 entry - "section" format (one-level paging, 1MB sized
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/** Page table level 0 entry - "section" format (one-level paging, 1MB sized
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 * pages). Used only for booting the kernel. */
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 * pages). Used only for booting the kernel. */
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typedef struct {
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typedef struct {
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    unsigned descriptor_type     : 2; // PTE_DESCRIPTOR_SECTION (0b10)
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    unsigned descriptor_type     : 2;
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    unsigned bufferable          : 1;
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    unsigned bufferable          : 1;
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    unsigned cacheable           : 1;
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    unsigned cacheable           : 1;
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    unsigned impl_specific       : 1;
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    unsigned impl_specific       : 1;
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    unsigned domain              : 4;
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    unsigned domain              : 4;
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    unsigned should_be_zero_1    : 1;
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    unsigned should_be_zero_1    : 1;
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    unsigned should_be_zero_2    : 8;
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    unsigned should_be_zero_2    : 8;
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    unsigned section_base_addr   : 12;
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    unsigned section_base_addr   : 12;
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} __attribute__ ((packed)) pte_level0_section;
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} __attribute__ ((packed)) pte_level0_section;
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/** Page table that holds 1:1 mapping for booting the kernel. */
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extern pte_level0_section page_table[PTL0_ENTRIES_ARCH];
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/** Starts the MMU - initializes page table and enables paging. */
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void mmu_start(void);
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/** Enables paging. */
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static inline void enable_paging()
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{
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    /* c3 - each two bits controls access to the one of domains (16)
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     *      0b01 - behave as a client (user) of a domain
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     */
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    asm volatile (
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        // behave as a client of domains
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        "ldr r0, =0x55555555       \n"
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        "mcr p15, 0, r0, c3, c0, 0 \n"
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        // current settings
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        "mrc p15, 0, r0, c1, c0, 0 \n"
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        /* TODO: talk to Alf why needed
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        // mask to disable aligment checks; system & rom bit set to 0 (has no
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        // special effect)
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        "ldr r1, =0xfffffe8f       \n"
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        "and r0, r0, r1            \n"
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        */
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        // mask to enable paging
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        "ldr r1, =0x00000001       \n"
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        "orr r0, r0, r1            \n"
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        // store settings
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        "mcr p15, 0, r0, c1, c0, 0 \n"
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        :
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        :
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        : "r0", "r1"
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    );
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}
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/** Sets the address of level 0 page table.
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/** Sets the address of level 0 page table.
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 * \param pt pointer to the page table to set
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 * \param pt pointer to the page table to set
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 */  
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 */  
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static inline void set_ptl0_address( pte_level0_section* pt) {
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static inline void set_ptl0_address(pte_level0_section* pt)
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{
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    asm volatile ( "mcr p15, 0, %0, c2, c0, 0 \n"
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    asm volatile ( "mcr p15, 0, %0, c2, c0, 0 \n"
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    :
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        :
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    : "r"(pt)
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        : "r"(pt)
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    );
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    );
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}
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}
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/** Page table that holds 1:1 mapping for booting the kernel. */
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extern pte_level0_section page_table[PTL0_ENTRIES_ARCH];
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/** Sets memory mapping for kernel */
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void mm_kernel_mapping(void);
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#endif
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#endif
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#endif
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#endif
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/** @}
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/** @}