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71 | /** Access rights to page table: user-no access, kernel-read/write */ |
71 | /** Access rights to page table: user-no access, kernel-read/write */ |
72 | #define PTE_AP_USER_NO_KERNEL_RW 1 |
72 | #define PTE_AP_USER_NO_KERNEL_RW 1 |
73 | 73 | ||
74 | #ifndef __ASM__ |
74 | #ifndef __ASM__ |
75 | 75 | ||
- | 76 | ||
76 | /** Page table level 0 entry - "section" format (one-level paging, 1MB sized |
77 | /** Page table level 0 entry - "section" format (one-level paging, 1MB sized |
77 | * pages). Used only for booting the kernel. */ |
78 | * pages). Used only for booting the kernel. */ |
78 | typedef struct { |
79 | typedef struct { |
79 | unsigned descriptor_type : 2; // PTE_DESCRIPTOR_SECTION (0b10) |
80 | unsigned descriptor_type : 2; |
80 | unsigned bufferable : 1; |
81 | unsigned bufferable : 1; |
81 | unsigned cacheable : 1; |
82 | unsigned cacheable : 1; |
82 | unsigned impl_specific : 1; |
83 | unsigned impl_specific : 1; |
83 | unsigned domain : 4; |
84 | unsigned domain : 4; |
84 | unsigned should_be_zero_1 : 1; |
85 | unsigned should_be_zero_1 : 1; |
Line 86... | Line 87... | ||
86 | unsigned should_be_zero_2 : 8; |
87 | unsigned should_be_zero_2 : 8; |
87 | unsigned section_base_addr : 12; |
88 | unsigned section_base_addr : 12; |
88 | } __attribute__ ((packed)) pte_level0_section; |
89 | } __attribute__ ((packed)) pte_level0_section; |
89 | 90 | ||
90 | 91 | ||
- | 92 | /** Page table that holds 1:1 mapping for booting the kernel. */ |
|
- | 93 | extern pte_level0_section page_table[PTL0_ENTRIES_ARCH]; |
|
- | 94 | ||
- | 95 | ||
- | 96 | /** Starts the MMU - initializes page table and enables paging. */ |
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- | 97 | void mmu_start(void); |
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- | 98 | ||
- | 99 | ||
- | 100 | /** Enables paging. */ |
|
- | 101 | static inline void enable_paging() |
|
- | 102 | { |
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- | 103 | /* c3 - each two bits controls access to the one of domains (16) |
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- | 104 | * 0b01 - behave as a client (user) of a domain |
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- | 105 | */ |
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- | 106 | asm volatile ( |
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- | 107 | // behave as a client of domains |
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- | 108 | "ldr r0, =0x55555555 \n" |
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- | 109 | "mcr p15, 0, r0, c3, c0, 0 \n" |
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- | 110 | // current settings |
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- | 111 | "mrc p15, 0, r0, c1, c0, 0 \n" |
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- | 112 | /* TODO: talk to Alf why needed |
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- | 113 | // mask to disable aligment checks; system & rom bit set to 0 (has no |
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- | 114 | // special effect) |
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- | 115 | "ldr r1, =0xfffffe8f \n" |
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- | 116 | "and r0, r0, r1 \n" |
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- | 117 | */ |
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- | 118 | // mask to enable paging |
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- | 119 | "ldr r1, =0x00000001 \n" |
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- | 120 | "orr r0, r0, r1 \n" |
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- | 121 | // store settings |
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- | 122 | "mcr p15, 0, r0, c1, c0, 0 \n" |
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- | 123 | : |
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- | 124 | : |
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- | 125 | : "r0", "r1" |
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- | 126 | ); |
|
- | 127 | } |
|
- | 128 | ||
- | 129 | ||
91 | /** Sets the address of level 0 page table. |
130 | /** Sets the address of level 0 page table. |
92 | * \param pt pointer to the page table to set |
131 | * \param pt pointer to the page table to set |
93 | */ |
132 | */ |
94 | static inline void set_ptl0_address( pte_level0_section* pt) { |
133 | static inline void set_ptl0_address(pte_level0_section* pt) |
- | 134 | { |
|
95 | asm volatile ( "mcr p15, 0, %0, c2, c0, 0 \n" |
135 | asm volatile ( "mcr p15, 0, %0, c2, c0, 0 \n" |
96 | : |
136 | : |
97 | : "r"(pt) |
137 | : "r"(pt) |
98 | ); |
138 | ); |
99 | - | ||
100 | } |
139 | } |
101 | 140 | ||
102 | /** Page table that holds 1:1 mapping for booting the kernel. */ |
- | |
103 | extern pte_level0_section page_table[PTL0_ENTRIES_ARCH]; |
- | |
104 | - | ||
105 | /** Sets memory mapping for kernel */ |
- | |
106 | void mm_kernel_mapping(void); |
- | |
107 | - | ||
108 | #endif |
141 | #endif |
109 | 142 | ||
110 | #endif |
143 | #endif |
111 | 144 | ||
112 | /** @} |
145 | /** @} |